Patents by Inventor Michel Cuenca

Michel Cuenca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220166415
    Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 26, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Vincent Binet, Michel Cuenca, Ludovic Girardeau
  • Publication number: 20220148962
    Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
  • Patent number: 11264324
    Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 1, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Samuel Boscher, Yann Rebours, Michel Cuenca
  • Publication number: 20210278868
    Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
  • Patent number: 10985750
    Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 20, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yohan Joly, Vincent Binet, Michel Cuenca
  • Patent number: 10958150
    Abstract: An electronic circuit includes a switched-mode power supply and a linear voltage regulation circuit having an input stage, a first output stage, and a second output stage. A first load is capable of being powered either by the switched-mode power supply in series with the regulation circuit or by the regulation circuit without the switched-mode power supply.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 23, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
  • Publication number: 20210028700
    Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Michel CUENCA, Sebastien ORTET
  • Publication number: 20200402902
    Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 24, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
  • Publication number: 20200395932
    Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 17, 2020
    Inventors: Yohan Joly, Vincent Binet, Michel Cuenca
  • Patent number: 10756628
    Abstract: An electronic circuit includes a switched-mode power supply powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and the gate of the transistor are capable of being coupled to a node of application of a power supply voltage. A method of operating the circuit is also disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 25, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Michel Cuenca, Cedric Thomas
  • Publication number: 20190372450
    Abstract: An electronic circuit includes a switched-mode power supply and a linear voltage regulation circuit having an input stage, a first output stage, and a second output stage. A first load is capable of being powered either by the switched-mode power supply in series with the regulation circuit or by the regulation circuit without the switched-mode power supply.
    Type: Application
    Filed: May 16, 2019
    Publication date: December 5, 2019
    Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
  • Publication number: 20190372460
    Abstract: An electronic circuit includes a switched-mode power supply powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and the gate of the transistor are capable of being coupled to a node of application of a power supply voltage. A method of operating the circuit is also disclosed.
    Type: Application
    Filed: May 9, 2019
    Publication date: December 5, 2019
    Inventors: Michel Cuenca, Cedric Thomas
  • Patent number: 10230363
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Publication number: 20170222639
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Inventors: Bruno Gailhard, Michel Cuenca
  • Patent number: 9654095
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Patent number: 9325325
    Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Publication number: 20150145564
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 28, 2015
    Inventors: Bruno Gailhard, Michel Cuenca
  • Publication number: 20150097630
    Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 9, 2015
    Inventors: Bruno Gailhard, Michel Cuenca
  • Patent number: 8854135
    Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Michel Cuenca, Laurent Truphemus
  • Patent number: 8471636
    Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 25, 2013
    Assignee: Atmel Rousset S.A.S.
    Inventors: Jimmy Fort, Thierry Soude, Michel Cuenca, Florent Garcia, Franck Strazzieri