Patents by Inventor Michel Cuenca
Michel Cuenca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097701Abstract: One embodiment provides a digital-to-analog converter that includes an output amplifier configured to be powered with a controllable power supply voltage and a ground reference voltage. The output amplifier is configured to generate an analog output signal having a dynamic range centered on a common-mode voltage. The output amplifier includes a common-mode adaptation circuit configured to position a level of the common-mode voltage at a level located in a middle portion of an interval of voltages located between the power supply voltage and the ground reference voltage, according to an effective level of the power supply voltage.Type: ApplicationFiled: September 8, 2023Publication date: March 21, 2024Inventors: Michel Cuenca, Didier Davino
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Publication number: 20230412076Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Michel CUENCA, Sebastien ORTET
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Patent number: 11784564Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.Type: GrantFiled: July 20, 2020Date of Patent: October 10, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Michel Cuenca, Sebastien Ortet
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Patent number: 11764151Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.Type: GrantFiled: January 20, 2022Date of Patent: September 19, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SASInventors: Samuel Boscher, Yann Rebours, Michel Cuenca
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Patent number: 11703897Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.Type: GrantFiled: March 5, 2020Date of Patent: July 18, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SASInventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Patent number: 11581880Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.Type: GrantFiled: November 11, 2021Date of Patent: February 14, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Vincent Binet, Michel Cuenca, Ludovic Girardeau
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Publication number: 20220166415Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.Type: ApplicationFiled: November 11, 2021Publication date: May 26, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Vincent Binet, Michel Cuenca, Ludovic Girardeau
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Publication number: 20220148962Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.Type: ApplicationFiled: January 20, 2022Publication date: May 12, 2022Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SASInventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
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Patent number: 11264324Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.Type: GrantFiled: June 15, 2020Date of Patent: March 1, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Samuel Boscher, Yann Rebours, Michel Cuenca
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Publication number: 20210278868Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Patent number: 10985750Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.Type: GrantFiled: May 28, 2020Date of Patent: April 20, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Yohan Joly, Vincent Binet, Michel Cuenca
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Patent number: 10958150Abstract: An electronic circuit includes a switched-mode power supply and a linear voltage regulation circuit having an input stage, a first output stage, and a second output stage. A first load is capable of being powered either by the switched-mode power supply in series with the regulation circuit or by the regulation circuit without the switched-mode power supply.Type: GrantFiled: May 16, 2019Date of Patent: March 23, 2021Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SASInventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Publication number: 20210028700Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.Type: ApplicationFiled: July 20, 2020Publication date: January 28, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Michel CUENCA, Sebastien ORTET
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Publication number: 20200402902Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.Type: ApplicationFiled: June 15, 2020Publication date: December 24, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
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Publication number: 20200395932Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.Type: ApplicationFiled: May 28, 2020Publication date: December 17, 2020Inventors: Yohan Joly, Vincent Binet, Michel Cuenca
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Patent number: 10756628Abstract: An electronic circuit includes a switched-mode power supply powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and the gate of the transistor are capable of being coupled to a node of application of a power supply voltage. A method of operating the circuit is also disclosed.Type: GrantFiled: May 9, 2019Date of Patent: August 25, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Michel Cuenca, Cedric Thomas
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Publication number: 20190372450Abstract: An electronic circuit includes a switched-mode power supply and a linear voltage regulation circuit having an input stage, a first output stage, and a second output stage. A first load is capable of being powered either by the switched-mode power supply in series with the regulation circuit or by the regulation circuit without the switched-mode power supply.Type: ApplicationFiled: May 16, 2019Publication date: December 5, 2019Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Publication number: 20190372460Abstract: An electronic circuit includes a switched-mode power supply powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and the gate of the transistor are capable of being coupled to a node of application of a power supply voltage. A method of operating the circuit is also disclosed.Type: ApplicationFiled: May 9, 2019Publication date: December 5, 2019Inventors: Michel Cuenca, Cedric Thomas
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Patent number: 10230363Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.Type: GrantFiled: April 18, 2017Date of Patent: March 12, 2019Assignee: STMicroelectronics (Rousset) SASInventors: Bruno Gailhard, Michel Cuenca
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Publication number: 20170222639Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Bruno Gailhard, Michel Cuenca