Abstract: A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available.

Abstract: Disclosed is a method of forming solder terminals for a pinless module, preferably for a pinless metallized ceramic module. The method is comprised of the following steps: forming a substrate having a pattern of conductors formed onto its top surface and preformed via-holes extending from the top to bottom surface; applying a droplet of flux at at least one of said preformed via-hole openings of the bottom surface of said substrate to fill said via-holes with flux by capillarity and form a glob of flux at the bottom openings; applying a solder preform, i.e.

Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..