Abstract: Input ECL level signals are received and converted into output CMOS level signals by input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) and is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of an input buffer circuit (20), which supplies two pairs of output signals (V1) V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The input buffer circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4 ) and one NFET (N1; N2) serially connected.