Abstract: A data processing system includes at least two processors, each having a cache memory containing an index section and a memory section. A first processor performs a task by deriving internal requests for its cache memory which also may respond to an external request derived from the other processor which is simultaneously processing a task. To avoid a conflict between the simultaneous processing of an internal request and of an external request by the same cache memory, one request may act on the other by delaying its enabling or by suspending its processing from the instant at which these requests are required to operate simultaneously on the index section or the memory section of the cache memory of the processor affected by these requests. Thereby, the tasks are performed by the system at an increased speed.

Abstract: Transfers of information items between a memory array and different processing units of a digital data processing system are managed. Interface unit DIM connected between the system memory array and coupling bus BUSA for the different processing units of the system, comprises buffers PB, RBO, RB1, respectively associated with circuits CA2, CA1 and CA3 for aligning information items. Transfers of information items relating to instructions and data pass through these buffers. The transfers are automatic as a function of space available in these buffers. The framing and length of the information items are controlled automatically by microfunctions which greatly simplify operations for the microprogrammer for the information items which are octet aligned and of variable length.