Abstract: A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit (CIN) and transmitting it to a subsequent circuit (COUT). The circuit includes a network which is formed by MOS transistors which can be programmed via programming lines and which supplies a logic combination. An exclusive carry-propagation-generation device is formed by three MOS transistors which are connected in series between a carry-propagation line and ground and whose gates are connected to one of the bits to be processed, to the logic combination, and to a carry inhibit line, respectively.

Abstract: The invention relates to a logic MOS gate of the domino type, having a precharging transistor, a validation transistor and logic transistors. To prevent unwanted discharging of a precharged high level, which may be induced by at least one input data being stabilized too slowly, that is to say not before a clock signal has risen to the high level, a p-MOS sub-network is arranged in parallel with the source-drain path of the precharging transistor and receives at least the input data which was too slowly stabilized in such a manner as to establish a conductor path which reestablishes the precharged high level.