Abstract: A testing apparatus for a high-frequency integrated circuit chip for transporting the high-frequency input/output signals of this circuit by means of high-frequency lines of adapted characteristics impedance to measuring apparatus, is characterized in that it comprises:a first subassembly constituted by an insulating or dielectric substrate carrying on the one hand the integrated circuit chip fixed on one of its surfaces and on the other hand a network of high-frequency lines of the coplanar type formed on the same surface (designated as front surface) and arranged according to a geometric configuration suitable to transport the signals emitted by the inputs/outputs of the integrated circuit to the peripheral regions of the substrate, and a second subassembly for receiving the substrate provided with the integrated circuit and with the co-planar network with, this second subassembly further having means for producing a pressure on the mass regions of the coplanar network on a mass surface of this second subas

Abstract: A testing apparatus for a high-frequency integrated-circuit chip contained in a leadless package, which enables the transmission of signals from n input/output contacts of the chip to measuring apparatus by means of high-frequency lines having a given characteristic impedance. The apparatus comprises a rigid dielectric plate having on a front surface a printed circuit forming a network of n high-frequency coplanar transmission lines having the given characteristic impedance. The apparatus includes first means for connecting n contacts of the package to n inputs of the coplanar transmission lines and second means for connecting n outputs of the transmission lines to coaxial high-frequency lines having the same given impedance, which supply the measuring apparatus.

Abstract: A clocked comparator comprising a comparison stage (1) for comparing an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF and supplying an intermediate signal V.sub.M and its complement V.sub.M, an amplifier stage ((2) for amplifying the logic states of the intermediate signal, a first latching stage (3) and a second latching stage (4) coupled to the comparison stage and to the amplifier stage respectively, for generating and storing the logic states determined by the signals from the comparison and amplifier stages. A second comparison stage (5) is coupled in parallel with the first comparison stage to compensate for hysteresis in said first comparison stage. A second amplifier stage (6) is coupled in parallel with the first amplifier stage to eliminate phase indeterminacy of the logic states of the intermediate signal. The second latching stage and the first latching stage are alternately enabled by a first clock signal C and its complement C.

Abstract: The invention relates to a method suitable for raising the breakdown voltage of a capacitor of the integrated circuit type formed on a semiconductor substrate and characterized in that the lower plate of the capacitor is under etched so that an air wedge is obtained. As a result of the air wedge, the electric current passed through the semiconductor material is lengthened and the breakdown phenomena at the edges of the capacitor are reduced. The invention also relates to capacitors obtained in this manner.