Patents by Inventor Michel Janus

Michel Janus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240353473
    Abstract: A computer-implemented method determines a quality state of a wafer. The method includes providing at least three process control monitoring metrics of the wafer. Each process control monitoring metric is collected on the wafer at a different process control monitoring coordinate. The method further includes inputting the at least three process control monitoring metrics and the different process control monitoring coordinates of the process control monitoring metrics into at least one machine learning algorithm, and outputting at least three approximated wafer level test values by the at least one machine learning algorithm. The method also includes determining the quality state of the wafer based on the at least three approximated wafer level test values.
    Type: Application
    Filed: April 18, 2024
    Publication date: October 24, 2024
    Inventors: Jonas Bergdolt, Maria Irina Nicolae, Michel Janus, Moritz Gronbach
  • Publication number: 20240264930
    Abstract: A computer-implemented method for determining a test sequence. The test sequence defines a sequential order of performing multiple tests on an instance of a product using stop-at-first-fail. One or more test data instances are accessed. A test data instance represents respective outcomes of the respective tests for an instance of the product. Test cost values are accessed representing costs of performing the respective tests. An optimization is performed of the sequential order. The optimization is configured to minimize an expected cost of performing the multiple tests according to the sequential order using stop-at-first-fail. The expected cost is determined from the one or more test data instances and the test cost values. Data is output representing the determined sequential order of the test sequence.
    Type: Application
    Filed: September 15, 2023
    Publication date: August 8, 2024
    Inventors: Sebastian Bayer, Michel Janus
  • Publication number: 20240264090
    Abstract: A method for fault analysis in wafers includes determining multiple wafer maps comprising indications of anomalies of the wafers, performing an evaluation based on the determined wafer maps, and performing the fault analysis based on the evaluation performed. Performing the evaluation includes multiple execution of a cluster analysis based on the determined wafer maps using different parameters, and identifying distinct clusters determined by the differently parameterized cluster analyses.
    Type: Application
    Filed: January 30, 2024
    Publication date: August 8, 2024
    Inventors: Waldemar Smirnov, Ralf Augke, Michel Janus, Thomas Schnitzler
  • Publication number: 20240055304
    Abstract: A method is for determining a reduced first amount of testing from a second amount of testing. The method includes provision of a binary matrix, and optimization of a cost function, which is dependent on test variables. Each of test of the second amount of testing is associated with a test variable, and the test variable characterizes whether the test is relevant. The cost function defines constraints: a first constraint is defined in that a result of a matrix/vector multiplication must be greater than or equal to a vector comprising only ones. The matrix of the matrix/vector multiplication is a matrix whose entries all have the value one. The entries of the binary matrix are subtracted, and the vector of matrix/vector multiplication is a vector comprising the test variables. A second constraint is defined in that the test variables are binary.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 15, 2024
    Inventors: Sebastian Bayer, Michel Janus
  • Publication number: 20230260056
    Abstract: A method predicts an expected waiting time for a route having a plurality of production operations in manufacturing. The method includes receiving a sorted list of production operations characterizing a route for manufacturing a lot, and defining a starting time point of a lot production start time. The method further includes, for each production operation in the sorted list, (i) sampling feature values for a plurality of features by sampling from a database of collected feature values for operation measured feature values based on the starting time point, wherein the features characterize a property and/or a state of the lot and/or a property and/or a state of a factory for manufacturing the lot, and (ii) predicting an expected waiting time of each production operation based on the sampled feature values. The expected waiting time of each production operation is accumulated to determine the expected waiting time for the route.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 17, 2023
    Inventors: Kai Schelthoff, Michel Janus
  • Publication number: 20230066599
    Abstract: A method determines an assignment rule in order to combine test results from different tests of the same semiconductor device. The method includes fitting a model, such as a linear regression model, using the model to predict the test data, calculating a cost matrix based on the predictions, and applying the Hungarian method to the cost matrix to obtain a new assignment rule and repeating these steps multiple times.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 2, 2023
    Inventors: Andreas Steimer, Eric Sebastian Schmidt, Mehul Bansal, Stefan Patrick Lindt, Csaba Domokos, Matthias Werner, Michel Janus