Abstract: A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for CNN applications that may be computationally intensive, requiring a huge number of convolution operations per second to process inputs such as video streams in real time.

Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Abstract: A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for CNN applications that may computationally intensive, requiring a huge number of convolution operations per seconds to process inputs such as video streams in real time.

Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Abstract: A processing system includes a plurality of processing resources capable of executing a plurality of objects. The objects include a client object and one or more server objects. The client object is capable of requesting a service provided by at least one of the one or more server objects. The processing system also includes a hardware object request broker capable of receiving one or more messages from the processing resource executing the client object and communicating the one or more messages to the processing resource executing at least one of the one or more server objects that provides the requested service. The one or more messages are capable of invoking the requested service.

Abstract: A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption.

Abstract: A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption.

Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing from/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.

Abstract: A processing system includes a plurality of processing resources capable of executing a plurality of objects. The objects include a client object and one or more server objects. The client object is capable of requesting a service provided by at least one of the one or more server objects. The processing system also includes a hardware object request broker capable of receiving one or more messages from the processing resource executing the client object and communicating the one or more messages to the processing resource executing at least one of the one or more server objects that provides the requested service. The one or more messages are capable of invoking the requested service.

Abstract: A method of scheduling in a switch for transferring data by information units is provided where the scheduling decisions are performed from the destination node point of view, considering the demand of all the source nodes to reach this destination node. This algorithm also allows an improvement in performance, from a traffic point of view, of a rotator switch, since the algorithm is much more fair than the known source based scheduling algorithm in sharing the bandwidth amongst the contenting source nodes for a given destination node. Embodiments of the invention, are extended to support class of service, including minimum bandwidth guarantee. Further embodiments are provided that support age-group to further increase the performance of a rotator switch fabric with respect to traffic.

Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing from/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.

Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing front/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.