Abstract: A method of controlling the supply of cells into an asynchronous network, comprises the steps of storing incoming bytes from multiple channels in respective channel buffers, creating in memory a timing event wheel partitioned into a plurality of sectors, of which one is active at any time, and placing cell pointers in the sectors. The cell pointers identify channel buffers and are distributed around the wheel in accordance with a desired transmission schedule. The wheel is stepwise advanced at a predetermined rate, and the cell pointers in the active sector are scanned at each advance of the wheel to identify the corresponding channel buffers. The bytes from the identified channel buffers are assembled into cells, which are forwarded for transmission over the asynchronous network. These are then multiplexed with VBR cells from another source.

Abstract: A high-speed bus system for a computer is constructed of a network of buses with parallel bit lines, each bus of which operates independently and supports serial packet communications, wherein transmit agents and receive agents associated with each communicating element in the bus system are connected to the bus system. Each transmit agent controls a single bus for transmission and each receive agent is connected to all other buses for reception in a diagonal topology. The architecture is based on use of a buffering element at each node in the bus structure, herein referred to as a cell bus interface (CBI) unit. Based on header data containing address information appended as part of a packet cell by a transmitting transmit agent, each receive agent decides whether the information provided on any bus is intended for it as a destination agent.