Abstract: A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.

Abstract: A quadrature modulator (QM) may be calibrated by determining total equivalent offsets in the I- and Q-channels, a total equivalent gain imbalance between the I- and Q-channels, and a total equivalent phase skew between the I- and Q-channels. These values may be obtained by taking various scalar measurements of the image to signal ratio (ISR) and carrier to signal ratio (CSR) of the QM, while alternatively altering the system gain imbalance, system phase skew, I-channel offset and Q-channel offset using a respective gain parameter, phase parameter, I-channel offset parameter, and Q-channel parameter. The gain and phase parameters may be defined in terms of the ISR, and the channel offset parameters may be defined in terms of the CSR. The system gain imbalance, system phase skew, and total offset in the channels may then be calculated based on the various ISR and CSR measurements.

Abstract: A quadrature modulator (QM) may be calibrated by determining total equivalent offsets in the I- and Q-channels, a total equivalent gain imbalance between the I- and Q-channels, and a total equivalent phase skew between the I- and Q-channels. These values may be obtained by taking various scalar measurements of the image to signal ratio (ISR) and carrier to signal ratio (CSR) of the QM, while alternatively altering the system gain imbalance, system phase skew, I-channel offset and Q-channel offset using a respective gain parameter, phase parameter, I-channel offset parameter, and Q-channel parameter. The gain and phase parameters may be defined in terms of the ISR, and the channel offset parameters may be defined in terms of the CSR. The system gain imbalance, system phase skew, and total offset in the channels may then be calculated based on the various ISR and CSR measurements.

Abstract: A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.