Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

Abstract: The method includes an adjustment phase in which a filtering device is operated as an oscillator, the frequency of oscillation of the filtering device is determined, and the characteristics of the filtering device are corrected with respect to the determined oscillation frequency and to a pre-established relation between the frequency of oscillation and the theoretical cutoff frequency, in such a way as to confer upon the filtering device a cutoff frequency equal to the theoretical cutoff frequency to within a tolerance. After the adjustment phase, a working phase takes place in which the filtering device carries out its filtering function.

Abstract: A controllable assembly of current sources includes several first output terminals, with a first transistor associated with each first output terminal, the current on each first output terminal depending on the current flowing through the first transistor, and a circuit configured, in response to a predetermined variation of a control voltage, to successively progressively turn on, then progressively turn off, each first transistor. The first transistors are MOS transistors, and each first output terminal is associated with a current mirror formed of MOS transistors, the current mirror providing to the first output terminal a current depending on the current flowing through the first transistor.

Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

Abstract: The method includes an adjustment phase in which a filtering device is operated as an oscillator, the frequency of oscillation of the filtering device is determined, and the characteristics of the filtering device are corrected with respect to the determined oscillation frequency and to a pre-established relation between the frequency of oscillation and the theoretical cutoff frequency, in such a way as to confer upon the filtering device a cutoff frequency equal to the theoretical cutoff frequency to within a tolerance. After the adjustment phase, a working phase takes place in which the filtering device carries out its filtering function.

Abstract: A controllable assembly of current sources including several first output terminals, a first transistor associated with each first output terminal, the current on each first output terminal depending on the current flowing through the first transistor, and a control means provided for, as a response to a predetermined variation of a control voltage, successively progressively turning on, then progressively turning off, each first transistor, in which the first transistors are MOS transistors, and in which each first output terminal is associated with a current mirror formed of MOS transistors, the current mirror providing to the first output terminal a current depending on the current flowing through the first transistor.

Abstract: A counter/divider dividing an input frequency (F1) by 2.sup.q+n +1/2, comprises a first divider by 2.sup.q (30) receiving the signal to divide of a frequency F1 and provides 2.sup.q+1 outputs at the frequency F1/2.sup.q out of phase the ones to the others of 360.degree./2.sup.q+1 ; a multiplexer (32) having a control terminal (34) and sequentially providng at its output (33) each of said 2.sup.q+1 outputs each time a control signal is applied; and a second divider by 2.sup.n (31) receiving the output (33) of the multiplexer and providing the desired output (34) of the counter/divider, this output being applied to the control terminal of the multiplexer.

Abstract: An N-bit interpolation analog/digital circuit comprises a first stage of p comparators (C.sub.1. . . C.sub.p). The outputs of the comparators are combined in a plurality of groups, which are connected so that the combined output (S.sub.1a, S.sub.1b) of each group has the shape of a signal periodically varying between high and low levels. The output voltages of each group are compared close to their zero crossings in second stages (I.sub.1. . . I.sub.r) of q+1 comparators each (p[q+1]=2.sup.N). Each comparator of the first stage is a high linearity comparator comprising two legs each comprising a first and a second transistor (T.sub.101, T.sub.102 ; T.sub.103, T.sub.104). The base of the second transistor of each leg is connected at the junction node of the transistors of the other leg through a voltage shifting means (E.sub.1, E.sub.2), and the emitters of the second transistors of each leg are interconnected through a resistor (RES).

Abstract: An output circuit compatible with TTL-type circuits, manufactured without Schottky devices comprises an intermediate stage (11) and an output stage (12). In the output stage, a first transistor (Q1) has its collector (C1) connected to the terminal (13) of the supply source through a resistor (R1) and its emitter (E1) connected to the output (S) through a diode (D1). A second transistor (Q2) has its collector (C2) connected to the output terminal (S) and its emitter (E2) connected to the terminal (14) of the supply source. A third transistor (Q3) has its emitter (E3) connected to the base (E2) of the second transistor (Q2) through a resistor (R4), its collector (C3) connected to the terminal (13) of the supply source and its base (B3) connected to the input terminal (A1). The intermediate stage is constituted by an inverter which controls the first transistor (Q1) in phase opposition with respect to the second transistor (Q2 ).