Abstract: A multiplexer module includes N input transistors (T.sub.0 to T.sub.3) whose bases receive input signals (E.sub.0 . . . E.sub.3), whose collectors are connected to ground and whose emitters are coupled to those of a multi-emitter output transister T'.sub.4. A logic addressing circuit (ALC) connects a current source I to one of the emitters of the input transistors (T.sub.0 to T.sub.3) as a function of an address (A.sub.0, A.sub.1) received. Any reference voltage on the output transistor (T'.sub.4) is suppressed by short-circuiting its base and its collector which constitutes the output S' which is connected to ground by way of an output resistor R'.sub.s. The module may be connected to other modules (having e.g. K inputs) within the same circuit, notably in order to realize a multiplexer having N.sup.k inputs without giving rise to stray coupling between the outputs of the various modules.

Abstract: A circuit for translating signal levels between a logic family type circuit (11) of, for example, the TTL type, and a second logic family type circuit of, for example, the ECL/CML type (12) of, for example, the ECL/CML type, in which a transit terminal (22) receives the output signals of the first logic circuit in order to translate them into input signals for the second logic circuit.The translator circuit comprises a transistor (T1) whose base is connected to a first point (P1) at a chosen potential, which may be common ground (M), via a first forward junction (J1), and is further connected to the transit terminal (22) by a series arrangement (23) of a resistor (R1) and a second junction (J2). The circuit further has a current source (S1) connected between the supply voltage source and the emitter of the transistor T1, and a load element (Z) for the current source (S1) connected to the emitter of the transistor T1 and to a second point (P2) at a chosen potential, which may be the common ground return.

Abstract: A programmable read-only memory includes a number of programmable memory cells, each of which is formed in a thin layer of semiconductor material which extends on an insulating layer of a semiconductor body. Each programmable memory cell includes a p-n junction diode and an electrically destructible programmation element which are integrally formed in the thin layer of semiconductor material. The programmation element includes a necked-down portion of the thin layer, and this element may also have a p-n junction. The resulting structure yields a memory cell which is simple, highly compact, and which can be easily and reliably manufactured by known methods.

Abstract: Integrated electrically programmable read only memory cell having at least two back-to-back diodes.A first diode is formed by a planar junction (7) between two superimposed regions (2, 6), the second diode is programmable and is formed by a lateral junction (11) between two coplanar zones (9, 10) of a thin semi-conductor layer isolated from the body by an insulating layer (8) having a contact aperture (18).

Abstract: A hysteresis threshold circuit including two complementary transistors and an output transistor with an injector controlled by the collector of the second complementary transistor. The emitters of the second transistor and of the output transistor are interconnected, while the input of the circuit is constituted by the emitter of the first complementary transistor.

Abstract: A read-only memory which can be programmed by means of internal fuses and whose memory cells are formed by bipolar transistors in an ECL circuit.The emitters of the memory-position transistors are coupled to the emitter in a row-address transistor, the bases are connected directly to the emitter of a column read transistor, the collector lines include the fuses, and the rows and columns are supplied from current sources.