Abstract: Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction.

Abstract: Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10 nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction.

Abstract: Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10 nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction.

Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.

Abstract: An electronic circuit assembly having at least one memory with error correction. The assembly has at least one memory with an error detection circuit and an error correction circuit. The error detection circuit is short-circuited if no error is detected by the detection circuit. The data read in the memory are transmitted directly to a first stage of the assembly and, at the same time, to the error detection and correction circuits. If the detection circuit detects an error, it controls transmission to the first stage, by use of a multiplexer, of the data corrected by the correction circuit and performs decontamination of the stages liable to have been contaminated by the erroneous data. Each stage has a latch, the detection circuit then also holds the latches of the successor stages until the data has been corrected in the first stage.

Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.

Abstract: The assembly comprises a circuit for detecting errors in data supplied by at least one of the blocks of the assembly. When an error has been detected, the assembly is decontaminated by one circuit for backup and reconstitution of past states of a latch associated to a block. The backup and reconstitution circuit comprises a multiplexer and buffer register. The multiplexer comprises a first input directly connected to the output of the latch and a second input connected to this output via the buffer register. A control circuit controls the buffer register and the multiplexer so as to activate the buffer register writing function and connect the output of the multiplexer to its first input at each cycle, during a normal operation phase, and to read enable the buffer register and connect the multiplexer output to its second input during predetermined cycles of a decontamination phase.

Abstract: The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.

Abstract: The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.

Abstract: The assembly comprises a circuit (3) for detecting errors in data supplied by at least one of the blocks of the assembly. When an error has been detected, the assembly is decontaminated by means of at least one circuit for backup and reconstitution of past states of a latch associated to a block. The backup and reconstitution circuit comprises a multiplexer (6) and a FIFO buffer register (5). The multiplexer comprises a first input directly connected to the output of the latch (2a) and a second input connected to this output via the buffer register. A control circuit (4) controls the buffer register and the multiplexer so as to activate the buffer register writing function and connect the output of the multiplexer to its first input at each cycle, during a normal operating phase, and the read enable the buffer register and connect the multiplexer output to its second input during predetermined cycles of a decontamination phase.

Abstract: The assembly comprises at least one memory (1) with an error detection circuit (5) and an error correction circuit (6). The error detection circuit is short-circuited if no error is detected by the detection circuit. The data read in the memory are transmitted directly to a first stage (3a, 4a) of the assembly and, at the same time, to the error detection and correction circuits. If the detection circuit detects an error, it controls transmission to the first stage, by means of a multiplexer (7), of the data corrected by the correction circuit (6) and performs decontamination of the stages liable to have been contaminated by the erroneous data. Each stage comprising a latch (4a, 4b . . . ), the detection circuit (5) then also holds the latches (4b, . . . ) of the successor stages until the data have been corrected in the first stage.