Abstract: Various exemplary embodiments relate to a method for controlling power consumption in a telecom system. The method includes selecting a power profile command based upon a desired power consumption and performance characteristic, translating the power profile command into at least one subcommand, and initiating at least one power reduction technique in a telecom component based upon the at least one subcommand.

Abstract: Various exemplary embodiments relate to a telecommunications system. The telecommunications system may include at least one actively operating component and at least one redundant component. The redundant component may include a first subcircuitry for receiving synchronization information and at least one second subcircuitry. The first subcircuitry may be activated independently of the second subcircuitry.

Abstract: Various exemplary embodiments relate to a telecommunications system. The telecommunications system may include at least one actively operating component and at least one redundant component. The redundant component may include a first subcircuitry for receiving synchronization information and at least one second subcircuitry. The first subcircuitry may be activated independently of the second subcircuitry.

Abstract: Various exemplary embodiments relate to a method for controlling power consumption in a telecom system. The method includes selecting a power profile command based upon a desired power consumption and performance characteristic, translating the power profile command into at least one subcommand, and initiating at least one power reduction technique in a telecom component based upon the at least one subcommand.

Abstract: Various embodiments relate to an in-system measurement of clock signals in a communications circuit. A circuit may include a central processing unit and at least one phase error counter (PEC) that uses a measurement clock to determine the accuracy of a target signal. In some embodiments, the PEC may include a counter that compares a clock signal produced by a reference oscillator with the signal of the measurement clock by generating an oscillator phase error based the measured difference during a target period. In some embodiments, the PEC may measure the performance of a clock recovery module by measuring a difference between a produced recovered clock signal and the measurement clock signal, which may be the clock recovery phase error between the two signals. The CPU may also use the measured phase errors to determine other values related to the target signal(s).

Abstract: A method and apparatus are provided for conveying low level signals from a first circuit card to a second circuit card. The low level signals are encoded using a simple integer value N, and the low level signals are then communicated to the second circuit card as a sequence of N alternating values. A binary counter is used to generate the sequence of alternating values using the output of a single pin of the counter, although a second pin may be used to generate a clock signal. The invention allows all low level signals to be communicated in a robust yet simple way, minimizing the chance of spurious signals being generated upon hot insertion or extraction without complicated ad hoc solutions.

Abstract: A method and apparatus are provided for conveying low level signals from a first circuit card to a second circuit card. The low level signals are encoded using a simple integer value N, and the low level signals are then communicated to the second circuit card as a sequence of N alternating values. A binary counter is used to generate the sequence of alternating values using the output of a single pin of the counter, although a second pin may be used to generate a clock signal. The invention allows all low level signals to be communicated in a robust yet simple way, minimizing the chance of spurious signals being generated upon hot insertion or extraction without complicated ad hoc solutions.

Abstract: A circuit card connector arrangement is provided, wherein one of the connectors on the card is recessed relative to the other connectors. Using this arrangement, insertion and extraction detection of the card into another card is optimized without the need for a short pin on the other card. The recessed connector is the last connector on the card to make electrical contact with the other card upon insertion and the first connector to lose electrical contact with the other card upon extraction. Since the degree of recess and the choice of which connector is recessed is made by the designer of the inserted card rather than dependent on the design of the main card or board, such as a backplane, onto which the card is inserted, greater flexibility is possible in the design of the card and of the insertion/extraction circuitry on the card. In addition, insertion and extraction can be detected even if the main board does not have a short pin, such as occurs in some legacy system.