Abstract: A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (19), a phase-locked loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input for controlling the value of its natural frequency, and the phase-locked loop (25) includes a counting circuit (30, 35) aggregating the relative values of the digital signal supplied by the digital phase detector (26) and supplying a control signal in digital form for the oscillator (19).

Abstract: A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (19), a phase-locked loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input for controlling the value of its natural frequency, and the phase-locked loop (25) includes a counting circuit (30, 35) aggregating the relative values of the digital signal supplied by the digital phase detector (26) and supplying a control signal in digital form for the oscillator (19).

Abstract: The present invention concerns a software system that tolerates transient errors made up by a processing unit, including: at least two processing units (50, 51) with each one including: a microprocessor (54, 57), a memory (53, 56) protected by a device generating and controlling a code for the detection and correction of errors, a device (55, 58) for monitoring memory accesses, A centralized control device (52) for the processing units and for inputs/outputs, including: macro-synchronization means, data comparison/vote means, correction demand means, decision-making means, means allowing the inputs/outputs to be made. Some links (60, 61) respectively linking each processing unit to the device (52) for controlling the processing units and the inputs/outputs.

Abstract: This invention relates to a processing procedure for an electronic system subject to transient error constraints, in which two virtual sequences installed on a single physical sequence are multiplexed in time in one given real time cycle (the data resulting from each execution of a virtual sequence being stored so that they can be voted before use), and in which if an error is detected, the real time cycle in progress is inhibited and a healthy context is reloaded to make a restart that consists of a nominal execution of the next cycle starting from the reloaded context. This invention also relates to a memory access monitoring device.

Abstract: The present invention concerns a software system that tolerates transient errors made up by a processing unit, including: