Abstract: Embodiments of the present disclosure generally relate to a film treatment process. In one embodiment, a transition metal oxide layer including a dopant is deposited on a substrate. After the doped transition metal oxide layer is deposited, a high pressure annealing process is performed on the doped transition metal oxide layer to densify the doped transition metal oxide without outgassing of the dopant. The high pressure annealing process is performed in an ambient environment including the dopant and at a pressure greater than 1 bar.

Abstract: Embodiments of the present disclosure generally relate to a film treatment process. In one embodiment, a transition metal oxide layer including a dopant is deposited on a substrate. After the doped transition metal oxide layer is deposited, a high pressure annealing process is performed on the doped transition metal oxide layer to densify the doped transition metal oxide without outgassing of the dopant. The high pressure annealing process is performed in an ambient environment including the dopant and at a pressure greater than 1 bar.

Abstract: Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing an adjustable or optimized laser patterning process to form openings with different geometry in a passivation layer disposed on a substrate based on different film properties in the passivation layer and the substrate. In one embodiment, a method of forming a solar cell includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, performing a substrate inspection process by a detector disposed in the laser patterning apparatus, determining a laser patterning recipe configured to form openings in the passivation layer based on information obtained from the substrate inspection process, and performing a laser patterning process on the passivation layer using the determined laser patterning recipe.

Abstract: The present invention generally relates to process testers and methods of fabricating the same using standard photovoltaic cell processes. In particular, the present invention relates to process tester layouts defined by laser scribing, methodology for creating process testers, methodology of using process testers for photovoltaic line diagnostics, placement of process testers in photovoltaic module production, and methodology for creating design rule testers.

Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Abstract: An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Abstract: Metalization structures are modeled by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections.

Abstract: A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.

Abstract: A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.