Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode.

Abstract: The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.

Abstract: A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).

Abstract: A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die.

Abstract: A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage. The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).

Abstract: The present invention relates to a method of forming a diode (2) for integration with a semiconductor device comprising the steps of providing a layer (4) of semiconductor material, forming a dielectric layer (6) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer (6), forming a semi-conductive layer (8) over the dielectric layer (6), introducing a second conductivity type dopant into a first region (12) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer (6) into the semi-conductive layer (8) so as to form a second region (18) of the first conductivity type dopant in the semi-conductive layer (8), the second region (18) being adjacent the first region (12) so as to provide a P/N junction of the diode (2).

Abstract: A semiconductor fuse device is formed of a conductive semiconductor substrate (11) having a top surface and a bottom surface. A layer (12) of dielectric material is provided on a portion of the top surface and a first conductive layer (15) is formed wholly on a first portion of the layer (12) of dielectric material and forms a first contact of the device. A second conductive layer (14) is formed on a second portion of the layer (12) of dielectric material spaced from the first portion and extends to contact the top surface of the substrate (11). A fuse portion (16) is formed wholly on the layer (12) of dielectric material and extends between and in electrical contact with the first and second conductive layers (14, 15). The bottom surface of the substrate (11) provides a second contact of the device, so that only one wire bond is necessary.

Abstract: A method for forming a semiconductor fuse device (23) having a fuse element (20) for an igniter device, comprises the steps of providing a semiconductor substrate (12), forming an insulator layer (14) on the semiconductor substrate, forming a single active layer (16) on the insulator layer, having a predetermined depth (18) of greater than 4 microns and patterning and etching the active layer to form the fuse element (20). Preferably, the forming a single active layer step includes the step of atomic bonding an active layer to the insulator layer.

Abstract: A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.