Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A PLL comprises a PFD, a loop filter and a VCO, as well as a voltage shift capacitor coupling the PFD and the VCO. A voltage shift control circuit is placed in parallel with the voltage shift capacitor. This circuit comprises controlled charging means, which are designed to charge the voltage shift capacitor according to a channel control signal. It also comprises controlled pre-charging means which are designed to accelerate the charging of the voltage shift capacitor by the controlled charging means. It further comprises controlled biasing means, designed to ensure the bias of the input during the pre-charging of the voltage shift capacitor.

Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.

Abstract: An oscillator (30) supplies a high frequency signal (S) to a frequency divider (31). A phase comparator (32) produces a signal measuring phase difference between the divided frequency signal (QA) and a reference signal. A low-pass filter (34) controls the oscillator on the basis of the measurement signal. A measurement window, of duration defined by counting cycles of the high frequency signal, is generated in response to each active edge of the divided frequency signal. The measurement signal is activated during the measurement window so that it comprises, when an active edge of the reference signal falls within the window, a first pulse between the start of the window and this edge and a second pulse, opposite to the first, between this edge and the end of the window.

Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.

Abstract: An oscillator (30) supplies a high frequency signal (S) to a frequency divider (31) . A phase comparator (32) produces a signal measuring phase difference between the divided frequency signal (QA) and a reference signal. A low-pass filter (34) controls the oscillator on the basis of the measurement signal. A measurement window, of duration defined by counting cycles of the high frequency signal, is generated in response to each active edge of the divided frequency signal. The measurement signal is activated during the measurement window so that it comprises, when an active edge of the reference signal falls within the window, a first pulse between the start of the window and this edge and a second pulse, opposite to the first, between this edge and the end of the window.

Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator and a second order second resonator, preferably of second order, whereof the respective central frequencies enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.

Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator (101) and a second order second resonator (102), preferably of second order, whereof the respective central frequencies are adjustable, so as to enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.

Abstract: The device forms first and second signals by mixing the input radio signal with two respective quadrature waves of frequency f.sub.O. An algebraic sum of these two signals is phase-shifted by .+-.45.degree. or .+-.135.degree. at an intermediate frequency f.sub.I. An output signal is formed by an algebraic sum between the phase-shifted signal and the first or second signal, in such a way that, at the intermediate frequency f.sub.I, the output signal has a phase representative of that possessed by the input radio signal at a communication frequency f.sub.C of the form f.sub.O -f.sub.I or f.sub.O +f.sub.I, with rejection of the phase of the input radio signal at the image frequency 2f.sub.O -f.sub.C.

Abstract: A first phase-locked loop (PLL) includes a first integrated voltage-controlled oscillator (VCO) whose output signal has a frequency modulated by an input signal of the device about a multiple of a reference frequency. A second PLL includes a second integrated VCO and frequency transposition means. The transposition circuit receive the output signal of the second VCO and a transposition signal having a non-modulated frequency. The second PLL addresses to the second VCO a control signal capable of aligning the frequency of the output signal of the transposition circuit with the frequency of the first VCO. The output signal of the second VCO forms the frequency modulation transmission signal produced by the device.

Abstract: In order to process an input signal exhibiting a frequency modulation about an intermediate frequency, the demodulator includes a first mixer for producing a first signal exhibiting the frequency modulation about a transposition frequency lower than the intermediate frequency; a switched-capacitor phase-shifter receiving the first signal so as to produce a second signal exhibiting, with respect to the first signal, a phase-shift varying substantially linearly with frequency about the transposition frequency; two substantially identical low-pass filters receiving the second signal and the first signal respectively; and a second mixer for mixing the signals produced by the first and second low-pass filters, in order to deliver a baseband output signal.