Abstract: Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

Abstract: A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inverter includes a complimentary pair of field-effect transistors (FETs). The second inverter includes either a complimentary pair of current mirrors, or a current mirror and a complimentary FET, the latter providing improved noise immunity characteristics when the soft latch is set in only one direction.

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

Abstract: A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.

Abstract: A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.

Abstract: According to the preferred embodiment, a buffer amplifier is provided that provides improved linearity while providing increased control over the gain without unduly limiting the amplifier frequency response. The amplifier preferably includes a series pair of transistors with their gates connected to the amplifier input and their drains connected to the amplifier output. The amplifier further includes a pair of feedback transistors connected in series with the series pair. The gates of the feedback transistors are connected to the amplifier output through a pair of feedback networks. Each network includes at least one impedance element. The impedance elements are preferably selected to maximize the linearity of the amplifier response. Furthermore, the impedance elements can be selected to modify the gain of the amplifier, increasing the amplifier gain if needed.