Abstract: Bit rate reservation is effected with the aid of a reservation cell containing a requested bit rate transmitted from a calling terminal to a called terminal via switching nodes of an asynchronous network. At each node, a bit rate increase request is at least partially satisfied even if the difference between the requested bit rate and the current bit rate is greater than the bit rate available at the node. The node replaces the requested bit rate in the reservation cell by a new bit rate lower than the latter so that the called terminal receives the lower new adopted bit rate by the nodes. An acknowledgement cell retransmitted with this lower new bit rate by the called terminal renders uniform the adopted bit rate at all the nodes. If no acknowledgement cell has been received after a predetermined time-delay the nodes revert to their initial state, with the current bit rate preceding the bit rate reservation.

Abstract: A process is described for spacing over time the transmissions of cells that belong to messages. The value of the address of the first cell of the message is stored in relation to the clock-time of the sending. At each time given by a local clock-time, the address value is read in relation to said local time. The cell having said address is sent. Then, the sending clock-time of the next cell of said message is computed. The address of the next cell of the message is determined. The address value of the next cell is stored in relation to the clock-time of its computed transmission. The invention also relates to spacing devices which are used to execute this process.

Abstract: A queueing circuit serves an asynchronous switching circuit. A number of input circuits are connected to inputs of a switching network in a one-to-one relationship with the outputs of the switching matrix. During its own time slot, each of the input circuit has a series of availability signals which are assigned to time slots that are later than the input circuit's own time slot. These availability signals indicate the availability condition at the matrix output for enabling an emission of a data cell during the time slot identified by the availability signal. Based upon the availability signal, the cell is released from a memory storage during an available one of the later time slots.

Abstract: A data transmission system has a time interval allocation system with a time interval management unit (UGIT) and a plurality of counters (CSO.sub.1 to CSO.sub.n) connected to one another in a cascaded series. The input of a counter (CSO.sub.i) is connected to the output of the preceding counter (CSO.sub.i-1) in the series. The input of the first counter (CSO.sub.1) is connected to the output of the time intervals management unit. Each counter (CSO.sub.i) is associated with an input carrying a time interval allocation demand signal (dem.sub.i) and provided with a command input for receiving the allocation demand signal (dem.sub.i) and delivering either the time interval value (ITin) present on its input if the allocation demand signal (dem.sub.i) is inactive, or the time interval value present on its input increased by a unit (ITin+1) if the demand signal (dem.sub.i) is active. The output of each counter (CSO.sub.i) is connected to the input of a register (RegAd.sub.

Abstract: A device for initiating multiple timings has a supply of clock pulses. At each clock pulse, an entering cell is stored in a communication system with asynchronous time switching. The stored cell belongs to a virtual communication circuit that carries a number in the label of the cell. A random access, read-write timing memory (MT) has a plurality of addressable zones which normally store null or inactive bits. The memory (MT) is alternately addressed for writing and for reading. The memory (MT) comprises a data input (ED) to store, in a zone addressed for writing, a parameter bound to a characteristic of a virtual circuit. A data output (SD) delivers the content of the memory zone addressed during reading.

Abstract: There is assigned to each virtual circuit a period (pm) corresponding to the theoretical minimum period between two consecutive cells of the virtual circuit and a maximum time limit (dm). The imaginary time of emission on the output multiplex of the last cell belonging to each virtual circuit is stored, and, upon the arrival of a new cell of a virtual circuit, a threshold time calculated by adding its actual time of arrival and the maximum time limit is compared with the imaginary time of emission expected of the new call in the course of being processed, the time being calculated by adding the imaginary time of emission of the last cell emitted and the minimum period (pm).

Abstract: The invention is a method of controlling asynchronous time-division communications. Cells received from an in-coming time division multiplex system are delivered to an out-going asynchronous time division multiplex system. Each in-coming cell is stored in a buffer memory at an address that corresponds to its re-sending time. At the time when the next cell of a particular communication arrives, the number of previously stored cells for that particular communication, that are stored in the buffer memory, is compared with a maximal number assigned to the particular communication. If the first number exceeds the second number, the next in-coming cell is not re-sent. Besides the buffer memory, the system includes a status memory and an arithmetic and logic unit. The status memory is divided into zones, each zone having two sections.

Abstract: The invention smooths asynchronous time communication outputs which are formed by cells received from an incoming synchronous time multiplex(XE) in order to supply an outgoing asynchronous time multiplex(XS). Each incoming cell is stored in a buffer memory (MT) with an address (Add) corresponding to the actual time when that cell will be transmitted (t) on the outgoing time multiplex (XS). The address (Add) of the cell entering the buffer memory (MT) is determined by calculating a function of the theoretical minimum time period (pm) between outgoing cells. The searching in the buffer memory (MT) is for the first free address (Add) corresponding to an actual transmission time (t) which is chronologically beyond the next theoretical transmission time (tso). The actual time for outgoing transmission is determined as a function of a period (pm) allotted to the communication to which the incoming cell belongs.

Abstract: The invention provides a method of measuring the load of a communication system, and more particularly of a multiplex switching network for asynchronous cells or packets. Each cell transmitted on the multiplex has a registered value which is divided by a predetermined number (N). The value forms the first operand (E2) of a subtraction and the result of the division forms the second operand (E1). A predetermined value is added to the result of the subtraction when the heading of the transmitted cell contains a particular identifier. A zero value is added in the contrary case. The result of the subtraction followed by the addition constitutes the new value which is to be recorded, which likewise represents the measurement of the load. The identifier identifies, for example, an occupied cell or a cell belonging to a given virtual circuit. A circuit for implementing the method is likewise described.

Abstract: A communication system is designed to equip an asynchronous time-division network and to enable terminals linked to the network to communicate in the no-connection mode. The system comprises a ring management device and components distributed among the terminals and interfacing the terminals with a virtual ring for managing the production, reception and transmission of data cells. The ring management device is linked via the network to each of the terminals in order to control the connection/disconnection requests coming from the terminals and to supply information concerning cell routing to the terminals linked to the ring. A terminal has a particular role as a pilot for regulating the rate of the data cells in the virtual ring. Another purpose of the pilot terminal is to eliminate the altered cells. Furthermore, there is provided in each of the terminals a device for limiting its rate to a maximum value.

Abstract: A system and process for controlling the flow of packets carried by asynchronous time multiplex (EPACi) channels. The packets from one communication link are identified by their label and the identity of the multiplex channels which carries them. The process is comprised of allocating for each communication a predetermined clock rate and a predetermined threshold value, measuring the difference between the number of packets entering belonging to the communication and the number of pulses generated by the clock, lower bounding this difference, and, if the difference reaches a predetermined threshold, triggering a signal (DEP) which causes the detection of packets belonging to the communication in question as long as the difference is not less than the predetermined threshold.

Abstract: A device embodying the invention for a packet time-division switcher comprises essentially a circuit for detecting beginnings and ends of load interruption periods in the switcher, and a period counter. The detecting circuit is connected to a plurality of input buffer quenes of the switcher and detects a load interruption when all queues signal a state of packet emptiness. A time base of the switcher is inhibited at the end of a period of predetermined duration established by the counter and following the detection of a load interruption. Said duration is predetermined so as to complete the switching of a packet that has been begun. Once the time base is inhibited, the operating of the switcher is interrupted and its power consumption becomes very low. The time base is freed as soon as a packet is received by the queues, and the switcher resumes operating.

Abstract: A first switching network embodying the invention is a subscriber installation having a chain structure. In the network, the switching is distributed over a plurality of switches each connecting a terminal to the network. A second embodiment is a business network having a star-chain structure and comprising a plurality of sub-networks of chain type. The sub-networks are star connected to central switches which operate in a load sharing mode. According to the method embodying the invention, the terminals connected to the network assume themselves the responsibility for determining communication routes through the network. During a communication set-up phase, caller and callee terminals transmit call packets which are disseminated to all terminals in order to measure two so-called "distances" respectively between the caller and the callee and between the callee and the caller. These distances are after included in data packets for routing said packets.

Abstract: The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.

Abstract: A system for switching information packets assigned with two levels of semantic priorities between entering time muliplex lines and outgoing time multiplex lines, the read address of a packet in a buffer memory of a switch being stored in a queueing file associated with an outgoing port intended to transmit the packet. The read address is accompanied by a bit which defines the priority level of the packet. Each queueing file is comprised of two zones in series between the input and the output. Means is included for writing in the first zone only when the second zone is full, the first zone is accessible only to high priority level packets between the reading of files. The rear addresses of low priority level packets, which were stored earlier than the read address of high priority level packet the oldest still being present in the file, is overwritten in equal number, at a maximum, to the number of read addresses stored in the first zone.

Abstract: A switching system for switching synchronous and/or synchronous data blocks between incoming and outgoing multiplexes. The asynchronous blocks are sporadically carried in the multiplexes. The cost of the system is reduced owing to the use of a single buffer memory whose cells memorize indifferently synchronous and asynchronous blocks. The number of cells is lower than the product of the number of incoming or outgoing multiplexes and the number of blocks per frame in the multiplexes. A buffer memory managing and write addressing circuit derives and memorizes the occupied or free condition of each of the buffer memory cells thereby permanently selecting the address of one of free buffer cells in which a data block is to be written. The occupied condition of a cell is signalled responsive to the write of an incoming data block into this cell, and the free condition of the cell is signalled responsive to the last read of the written block.

Abstract: An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.

Abstract: The method consists in converting an inputting multiframe including of M frames each having words assigned respectively to C multiplexed digital channels into an outgoing multiframe including of C packets each having M words of a respective channel. So as to only use a single memory, a word having a given rank in the outgoing multiframe and a word having said given rank in the inputting multiframe are read and written consecutively in a same cell of the single memory. The memory has a capacity at least equal to MC word cells. The MC cells are addressed according to an address order rebecoming identical to itself after a cycle of N multiframe periods, where N is the smallest integer so that C.sup.N .tbd.1 (mod (MC-1)).

Abstract: A memory arrangement for temporary data storage of the FIFO type includes a random access memory associated with an input buffer register and two output buffer registers. The registers may consist of transparent flip-flops. The control system for the arrangement is provided for authorizing reading out from the output register at any time independently of the writing times in the random access memory and for causing reading out from the random access memory in response to an indication that the first output register is empty. A priority input of said control system makes it possible to interrupt a reading or writing operation when a request for the other operation is received. The control system has means for detecting full condition and empty condition of the FIFO. The control system further includes a handling logic for the output registers.

Abstract: The system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of each incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction.