Patents by Inventor Michel Vallet

Michel Vallet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7196421
    Abstract: An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a plurality of non-parallel rectangles in mutual contact. In one embodiment, the at least one dummy conductor is in the form of an “L”. In another embodiment, the at least one dummy conductor is in the form of a Latin cross. In yet another embodiment, the at least one dummy conductor is in the form of a “T”.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: March 27, 2007
    Assignee: STMicroelectronics SA
    Inventor: Michel Vallet
  • Publication number: 20060157699
    Abstract: A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and the front side of the integrated circuit. This tunnel is designed to channel photons emitted by the switching element towards the front side.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 20, 2006
    Applicant: STMicroelectronics SA
    Inventors: Michel Vallet, Philippe Sardin, Thierry Parrassin, Sylvain Dudit
  • Publication number: 20050029661
    Abstract: An integrated circuit is provided that includes an active region and at least one interconnect part. The interconnect part is located above the active region, and includes a plurality of metallization levels and at least one test pad. The test pad is located in one of the metallization levels that is beneath a top one of the metallization levels. In a preferred embodiment, the test pad is located beneath supply lines. Also provided is a method for testing such an integrated circuit.
    Type: Application
    Filed: May 5, 2004
    Publication date: February 10, 2005
    Applicant: STMICROELECTRONICS SA
    Inventors: Michel Vallet, Sylvain Kritter
  • Publication number: 20050006772
    Abstract: An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a plurality of non-parallel rectangles in mutual contact. In one embodiment, the at least one dummy conductor is in the form of an “L”. In another embodiment, the at least one dummy conductor is in the form of a Latin cross. In yet another embodiment, the at least one dummy conductor is in the form of a “T”.
    Type: Application
    Filed: May 5, 2004
    Publication date: January 13, 2005
    Applicant: STMICROELECTRONICS SA
    Inventor: Michel Vallet
  • Patent number: 6539276
    Abstract: A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit. Also provided is a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: March 25, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Michel Vallet
  • Patent number: 6382990
    Abstract: The invention provides for an electrical connection socket including an insulating block comprising a central protuberance. A plurality of peripheral contact housings are arranged in the insulating block. Each peripheral contact housing includes an electrical contact. Each peripheral contact is adapted to mate with a corresponding pin when the electrical connection socket is coupled to an electrical connection plug. A safety disk is provided having a central opening and at least a same number of peripheral through openings as there are electrical contacts. The central opening of the safety disk is adapted to receive at least a portion of the central protuberance of the insulating block. The safety disk is rotatably mounted to the insulating block so as to form explosive proof joint between at least two surfaces.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: May 7, 2002
    Assignee: Societe d'Exploitation des Procedes Marechal (SEPM)
    Inventors: Gilles Marechal, Jean-Michel Vallet
  • Patent number: 6246072
    Abstract: The present invention relates to an integrated circuit test pad implemented in a surface metallization layer covered with an insulating coating. The pad is surrounded with a first metal ring made in the surface metallization layer and with a second metal ring made in a lower metallization surface, the first and second rings being electrically interconnected by at least one via and set to a fixed potential.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: June 12, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Michel Vallet
  • Patent number: 6211688
    Abstract: The invention relates to a test area of an electronic circuit comprising a contact point formed in the surface of a substrate. The test area also includes spaced apart radially extending bosses adjacent the contact point for guiding a test probe positioned on the surface of the substrate to the contact point.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Michel Vallet
  • Patent number: 6175240
    Abstract: DC voltage levels applied to an integrated circuit are measured using an electron beam. A pulsed signal having a peak voltage dependent upon or representing one of the DC voltage level applied to the integrated circuit is first generated. The pulsed signal is applied to a test zone, and the voltage of the test zone varies according to the pulsed signal. The DC voltage level applied to the test zone on the integrated circuit transforms into a pulsed voltage. An electron beam is then used to measure the voltage of the test zone.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: January 16, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Michel Vallet
  • Patent number: 5897387
    Abstract: Electrical waterproof coupler socket is provided with a body including housings containing contacts and openings for passage of opposing contacts of another device. A protective flap is translationally slidably mounted on the body and includes apertures arranged in a same number and manner as the openings of the body, and includes at least one blocking zone. The flap is slidable between at least one blocking position where the at least one blocking zone blocks the openings, and an opening position where the openings and apertures are superimposed, with the at least one blocking zone comprising a plane that is inclined towards the opposing surface of the flap from front-to-rear with respect to the direction in which the flap translates towards the opening position.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: April 27, 1999
    Assignee: Societe d'Exploitation des Procedes Marechal (SEPM) s.a.
    Inventors: Jean-Michel Vallet, Pierre Willams
  • Patent number: 5127749
    Abstract: A method of repairing a spent printhead or printhead subassembly and a repaired printhead or printhead subassembly made in accordance with such method is disclosed. The method includes the steps of removing the print pins from the spent printhead or printhead subassembly, removing at least a portion of the nose section in the area of the print pin holes of the spent printhead or printhead subassembly, filling at least a portion of such removed portion of the nose section with a casting material, inserting guide wires into the print pin holes in the nose section and permitting the casting material to at least partially cure to form new print pin holes.
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: July 7, 1992
    Assignee: Depot America, Inc.
    Inventors: John A. Tiano, Jr., Michel Vallet, Joseph L. Costa