Abstract: An array of photodetector is organized along a first organizational axis on a semiconductor substrate of a first conductivity type. Each photodetector is at least partially formed in the substrate which forms a first electrode of the photodetector. A peripheral polarization ring is formed around the array of photodetectors. The polarization ring is connected to a polarization voltage generator and to the substrate. A read circuit is connected to a photodetector via the second terminal of the photodetector. A first switch connects the photodetector to a generator of an additional voltage. A second switch connects the photodetector to the associated read circuit. The first and the second switches are in opposite states.

Abstract: An array of photodetector is organized along a first organizational axis on a semiconductor substrate of a first conductivity type. Each photodetector is at least partially formed in the substrate which forms a first electrode of the photodetector. A peripheral polarization ring is formed around the array of photodetectors. The polarization ring is connected to a polarization voltage generator and to the substrate. A read circuit is connected to a photodetector via the second terminal of the photodetector. A first switch connects the photodetector to a generator of an additional voltage. A second switch connects the photodetector to the associated read circuit. The first and the second switches are in opposite states.

Abstract: In an infrared detector provided with a photodiode, when the temperature of the photodiode is lowered to its operating temperature, the photodiode is forward biased. During forward biasing of the photodiode, injection of a majority carrier current takes place through the photodiode. The majority carriers mask a part of the defects of the photodiode. The acquisition phase is then performed by reverse biasing the photodiode.

Abstract: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.

Abstract: The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: In an infrared detector provided with a photodiode, when the temperature of the photodiode is lowered to its operating temperature, the photodiode is forward biased. During forward biasing of the photodiode, injection of a majority carrier current takes place through the photodiode. The majority carriers mask a part of the defects of the photodiode. The acquisition phase is then performed by reverse biasing the photodiode.

Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

Abstract: A semiconductor switch arrangement comprises a bipolar transistor and a semiconductor power switch having an input node, an output node and a control node for allowing a current path to be formed between the input node and the output node. The bipolar transistor is coupled between the input node and the control node such that upon receiving an electro-static discharge pulse the bipolar transistor allows a current to flow from the input node to the control node upon a predetermined voltage being exceeded at the input node to allow the control node to cause a current to flow from the input node to the output node. Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.

Abstract: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.

Abstract: The invention relates to a device for reading electronic charges, comprising an input for receiving the electronic charges, at least one capacitor for storing the electronic charges and at least one circuit based on MOS transistors, whereof the maximum operating voltage determines the maximum voltage at the terminals of the at least one capacitor (20, 38), and wherein the or each MOS transistor-based circuit is constituted by cascode-mounted transistors.

Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

Abstract: The present invention relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: A semiconductor switch arrangement (300) comprises a bipolar transistor (302) and a semiconductor power switch (301) having an input node (306), an output node (304) and a control node (305) for allowing a current path to be formed between the input node (306) and the output node (307). The bipolar transistor (302) is coupled between the input node (306) and the control node (305) such that upon receiving an electro-static discharge pulse the bipolar transistor (302) allows a current to flow from the input node (306) to the control node (305) upon a pre-determined voltage being exceeded at the input node (306) to allow the control node (305) to cause a current to flow from the input node (306) to the output node (307). Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.

Abstract: An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vtl for ESD protection. Vtl can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.

Abstract: A voltage protection device comprising an integrated circuit associated with a first voltage variable element and a second voltage variable element; wherein the first voltage variable element has a first voltage variable characteristic and the second voltage variable element has a second voltage variable characteristic such that the first voltage variable element and the second voltage variable element have different voltage variable characteristics for allowing the first voltage variable element to provide voltage protection to the integrated circuit at a first voltage and the second voltage variable element to provide voltage protection to the integrated circuit at a second voltage.

Abstract: An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vt1 for ESD protection. Vt1 can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.