Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system.