Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current for the programming currents into the common control node.

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

Abstract: A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica.

Abstract: A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents in

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: Secure vehicular communication is described herein. An example apparatus can include a processor and a vehicular communication component. The vehicular communication component can be configured to generate a vehicular private key and a vehicular public key, provide the vehicular public key to a plurality of external communication components wherein each respective one of the plurality of external communication components is positioned on a different transportation assistance entity, provide data to at least one of the plurality of external communication components, receive, in response to providing the data, additional data from the at least one of the plurality of external communication components, wherein the additional data is encrypted using the vehicular public key, and decrypt the additional data using the vehicular private key.

Abstract: Secure vehicular communication is described herein. An example apparatus can include a processor and a vehicular communication component. The vehicular communication component can be configured to generate a vehicular private key and a vehicular public key, provide the vehicular public key to a plurality of external communication components wherein each respective one of the plurality of external communication components is positioned on a different transportation assistance entity, provide data to at least one of the plurality of external communication components, receive, in response to providing the data, additional data from the at least one of the plurality of external communication components, wherein the additional data is encrypted using the vehicular public key, and decrypt the additional data using the vehicular private key.

Abstract: A method implemented in a computing device includes: generating an initial key from key injection or based on a value provided by at least one physical unclonable function (PUF); generating an obfuscated key based on the initial key; and storing the obfuscated key in a non-volatile memory.

Abstract: Secure vehicular communication is described herein. An example apparatus can include a processor and a vehicular communication component. The vehicular communication component can be configured to generate a vehicular private key and a vehicular public key, provide the vehicular public key to a plurality of external communication components wherein each respective one of the plurality of external communication components is positioned on a different transportation assistance entity, provide data to at least one of the plurality of external communication components, receive, in response to providing the data, additional data from the at least one of the plurality of external communication components, wherein the additional data is encrypted using the vehicular public key, and decrypt the additional data using the vehicular private key.

Abstract: A method implemented in a computing device includes: generating an initial key from key injection or based on a value provided by at least one physical unclonable function (PUF); generating an obfuscated key based on the initial key; and storing the obfuscated key in a non-volatile memory.