Abstract: A collection tool comprises a drive chassis, a harvester module disposed on the drive chassis, the harvester module including a vision system configured to identify target objects, and a robotic arm including a grasper configured to collect the target objects, and a subsystem including an articulating semi-rigid catch member, the semi-rigid catch member configured to transition into a retracted state while the drive chassis is in motion and to transition into an extended state while the drive chassis is stationary and the robotic arm is in a process of collecting the target objects.

Abstract: A method for executing programs (P) in an electronic system for applications provided with functional safety that includes a single-processor or multiprocessor processing system and a further independent control module, the method comprising: performing an operation of breaking-down of a program (P) into a plurality of parallel sub-programs (P1, . . . , Pn); assigning execution of each parallel sub-program (P1, . . . , Pn) to a respective processing module of the system, periodically performing self-test operations (Astl, Asys, Achk) associated to each of said sub-programs (P1, . . . , Pn).

Abstract: A method for executing programs (P) in an electronic system for applications provided with functional safety that includes a single-processor or multiprocessor processing system and a further independent control module, the method comprising: performing an operation of breaking-down of a program (P) into a plurality of parallel sub-programs (P1, . . . , Pn); assigning execution of each parallel sub-program (P1, . . . , Pn) to a respective processing module of the system, periodically performing self-test operations (Astl, Asys, Achk) associated to each of said sub-programs (P1, . . .

Abstract: A heartbeat monitoring circuit shares one electrode with another device, such as a biometric sensor, and a second electrode that may be a dedicated element or form a part of the case of the apparatus in which the circuit is housed. When operated as an electrode for the heartbeat monitoring circuit, the biometric sensor is contacted by the user's finger while the second electrode is contacted by another part of the user's body, such as a finger on the hand holding the apparatus (e.g., cell phone). Contact may then simply and naturally be made on either side of the user's heart, and ideal arrangement for parametric heart data acquisition. A third electrode may optionally be provided. Data analysis may be performed on the apparatus or by a remote optional processing center.

Abstract: A protocol-based communication between a host device (e.g., MP3 player, digital camera, palmtop, etc.) and an interface (e.g., flash mass storage card) is established automatically by providing protocol-supporting facilities in the interface, each facility supporting communication with the host device based on a respective protocol, by sending a query message from the host device to the interface specifying at least one protocol for use in protocol-based communication, by searching, within the plurality of protocol-supporting facilities provided in the interface one protocol-supporting facility supporting the protocol proposed in the query message, and if such protocol-supporting facility is found within the plurality of protocol-supporting facilities provided in the interface, by setting up the protocol-based communication between the host device and the interface based on the protocol proposed in the query message issued from the host device.

Abstract: A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Abstract: A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.

Abstract: An electronic system supporting modular expansion of its functions is of a type including a portable host electronic device associated with an expansion module adapted for quick-connect engagement and disengagement in/from the portable device. The expansion module includes a series of peripheral devices adapted to serve different classes of functions; a non-volatile memory storing information that pertains to configuring the different functions in the module; a re-configurable device adapted to establish connections, implement functional portions, and control all the system components; a control device adapted to cooperate with the host device in guiding the steps for re-configuring the whole system; and a software algorithm adapted to instruct the system to re-configure itself on which function and with which characteristics.

Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 ?m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 ?m2.

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: A protocol-based communication between a host device (e.g., MP3 player, digital camera, palmtop, etc.) and an interface (e.g., flash mass storage card) is established automatically by providing protocol-supporting facilities in the interface, each facility supporting communication with the host device based on a respective protocol, by sending a query message from the host device to the interface specifying at least one protocol for use in protocol-based communication, by searching, within the plurality of protocol-supporting facilities provided in the interface one protocol-supporting facility supporting the protocol proposed in the query message, and if such protocol-supporting facility is found within the plurality of protocol-supporting facilities provided in the interface, by setting up the protocol-based communication between the host device and the interface based on the protocol proposed in the query message issued from the host device.

Abstract: An electronic system supporting modular expansion of its functions is of a type including a portable host electronic device associated with an expansion module adapted for quick-connect engagement and disengagement in/from the portable device. The expansion module includes a series of peripheral devices adapted to serve different classes of functions; a non-volatile memory storing information that pertains to configuring the different functions in the module; a re-configurable device adapted to establish connections, implement functional portions, and control all the system components; a control device adapted to cooperate with the host device in guiding the steps for re-configuring the whole system; and a software algorithm adapted to instruct the system to re-configure itself on which function and with which characteristics.

Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.

Abstract: A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Abstract: The invention relates to a method of expanding the functional capabilities of portable electronic devices with user friendly modes, wherein a host device is associated a quick-connect function-expanding module. In this method, at each installation of a given module, the functional expansion module and the host device recognize each other; on first installation of a given module in the host device, a series of checking operations are carried out automatically; the user can select to activate the available expansion; and once a given application is selected, the configuration and functions required for each application are stored.

Abstract: A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 ?m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 ?m2.

Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.