Abstract: A shared ledger of transactions may be used for various purposes and may be later accessed by interested parties for ledger verification. Authenticity of transactions requires active measures to ensure transaction participants including parties to the transactions, observers to the transaction, etc., are providing accurate information for each transaction.

Abstract: A shared ledger of transactions may be used for various purposes and may be later accessed by interested parties for ledger verification. Authenticity of transactions requires active measures to ensure transaction participants including parties to the transactions, observers to the transaction, etc., are providing accurate information for each transaction.

Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).

Abstract: Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.

Abstract: Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.

Abstract: Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.

Abstract: Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).