Patents by Inventor Michele Incarnati
Michele Incarnati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955204Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: GrantFiled: October 3, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Publication number: 20240071510Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda, Jeffrey S. McNeil, Umberto Siciliani, Daniel J. Hubbard, Walter Di Francesco, Michele Incarnati
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Publication number: 20230105956Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: ApplicationFiled: October 3, 2022Publication date: April 6, 2023Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Patent number: 11550717Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: GrantFiled: August 22, 2019Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Patent number: 11462250Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: GrantFiled: August 5, 2020Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Patent number: 11061762Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.Type: GrantFiled: February 4, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Naveen Prabhu Vittal Prabhu, Bharat M. Pathak, Aliasgar S. Madraswala, Yogesh B. Wakchaure, Violante Moschiano, Walter Di Francesco, Michele Incarnati, Antonino Giuseppe La Spina
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Publication number: 20210090623Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: ApplicationFiled: August 5, 2020Publication date: March 25, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Patent number: 10922220Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: GrantFiled: July 1, 2017Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Patent number: 10891187Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.Type: GrantFiled: July 19, 2019Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
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Patent number: 10891188Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.Type: GrantFiled: July 19, 2019Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
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Patent number: 10755755Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: GrantFiled: August 22, 2018Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Publication number: 20200250028Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.Type: ApplicationFiled: February 4, 2019Publication date: August 6, 2020Inventors: Naveen Prabhu VITTAL PRABHU, Bharat M. PATHAK, Aliasgar S. MADRASWALA, Yogesh B. WAKCHAURE, Violante MOSCHIANO, Walter DI FRANCESCO, Michele INCARNATI, Antonino Giuseppe LA SPINA
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Publication number: 20190377675Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Publication number: 20190340066Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
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Publication number: 20190340065Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
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Patent number: 10409673Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.Type: GrantFiled: January 25, 2017Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
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Patent number: 10402319Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: GrantFiled: July 25, 2014Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Publication number: 20190004938Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Publication number: 20180366167Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).Type: ApplicationFiled: August 22, 2018Publication date: December 20, 2018Inventors: Theodore T. Pekny, Jae-Kwan Park, Violante Moschiano, Michele Incarnati, Luca de Santis
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Patent number: 10134481Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.Type: GrantFiled: March 3, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini