Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.

Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.

Abstract: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

Abstract: A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of the CMOS logic portion with the PCM portion is described.

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.

Abstract: A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

Abstract: A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of the CMOS logic portion with the PCM portion is described.

Abstract: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

Abstract: A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

Abstract: A phase change memory includes a cup-shaped heater element formed above a body. A tapered phase change region is formed on the cup-shaped heater element. The cup-shaped heater element is formed by depositing a stop layer of a first dielectric material over the body. A first sacrificial layer is deposited over the stop layer, the first sacrificial layer being of a second dielectric material that can be etched selectively with respect to the first dielectric material. An opening is etched in the first sacrificial layer and the stop layer. A heating layer is formed in the opening. The opening is filled with a filling material to obtain a structure having a cup-shaped heating region formed in the stop layer and excess portions extending over said stop layer. The excess portions by an etch selective with respect to the first dielectric material are removed.

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.