Abstract: A detection circuit may be configured to receive an input signal indicative of a data state and to detect the data state using charge sharing between two capacitors to achieve detection with threshold compensation . The detection circuit may include semi-latch circuitry and boosting circuitry to expedite the detection, thereby achieving high speed at low power consumption and low circuit size.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device controls a power supply to a detector that is used to sense a voltage of a bitline coupled to a memory cell. An output of the detector indicates a logic state of the selected memory cell. By controlling a voltage of the power supply, a detection threshold of the detector can be increased as the voltage on the bitline increases. This permits the detector to be used without requiring precharge of the bitline.

Abstract: Systems, methods, and apparatus related to unity buffers in memory devices. In one approach, a memory device includes memory arrays having memory cells. The memory device includes access lines to access the memory cells. The memory device includes unity buffers to drive the access line loads. Each buffer has an output current limiter that limits current flow when driving a voltage on the access lines. By limiting the current, the current limiter provides improved frequency response and operating stability for the buffer without the need for a compensation net.

Abstract: Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a differential read operation is performed on a memory cell pair. Bitlines or digit lines are used to select the memory cells. The read operation is performed in a subthreshold mode in which the memory cells of the pair do not threshold (e.g., do not switch or snap). A voltage on a wordline used to select the memory cell pair is ramped to increasing magnitudes of voltage while the bitline or digit line voltages are held fixed. One or more detectors are used to determine a difference in leakage currents of the two memory cells. A logic state is determined (e.g., using at least one detector) based on the difference in leakage currents. A feedback circuit reduces voltages applied to the bitlines or digit lines in order to avoid thresholding the cells. The voltage reduction by the feedback circuit is triggered when the reading of the memory cell pair is complete.

Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

Abstract: Methods, systems, and devices for sensing component with a common node are described. A set of sense circuits of a memory device may include a shared differential amplifier having a first branch for each sense circuit and a shared second branch, as well as a shared common node. A respective latch of each sense amplifier may be initialized to a second logic state, and the common node may undergo a voltage ramp to determine the state stored in the memory cell. If the memory cell stores the first logic state, the sense amplifier may couple with the common node to draw the current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state the current may not be drawn and the state of the latch may not switch.

Abstract: Methods, systems, and devices for sensing component with a common node are described. A set of sense circuits of a memory device may include a shared differential amplifier having a first branch for each sense circuit and a shared second branch, as well as a shared common node. A respective latch of each sense amplifier may be initialized to a second logic state, and the common node may undergo a voltage ramp to determine the state stored in the memory cell. If the memory cell stores the first logic state, the sense amplifier may couple with the common node to draw the current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state the current may not be drawn and the state of the latch may not switch.

Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.