Patents by Inventor Michele Quarantelli

Michele Quarantelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
    Publication number: 20090140762
    Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.
    Type: Application
    Filed: February 10, 2009
    Publication date: June 4, 2009
    Applicant: PDF Solutions, Inc.
    Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
  • Layout for DUT arrays used in semiconductor wafer testing
    Patent number: 7489151
    Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 10, 2009
    Assignee: PDF Solutions, Inc.
    Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
  • Layout for DUT arrays used in semiconductor wafer testing
    Publication number: 20070075718
    Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 5, 2007
    Applicant: PDF Solutions, Inc.
    Inventors: Christopher Hess, Angelo Rossoni, Stefano Tonello, Michele Squicciarini, Michele Quarantelli
  • Sensing circuit for memory cells
    Patent number: 6535428
    Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: March 18, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi
  • BIASING CIRCUIT FOR MULTI-LEVEL MEMORY CELLS
    Publication number: 20020196664
    Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
    Type: Application
    Filed: June 14, 2001
    Publication date: December 26, 2002
    Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi