Abstract: The invention is a portable electronic device comprising a non volatile memory and a memory controller. The portable electronic device comprises a connector having eight pads able to communicate using a protocol of Secure Digital® type. The connector comprises at least one additional pad intended to be linked to an antenna. The additional pad is able to communicate using a protocol of SWP type.

Abstract: A boot sequence method comprises a determination step 110 and 200, a first starting step 120, 210 or 240 for starting a first interface, a first negotiation step 140 or 220 wherein a power negotiation is performed, a second negotiation step 140 or 230 for determining the interfaces to activate simultaneously, and a second starting step 150 or 230 wherein the interfaces that can be activated simultaneously are started one after each other.

Abstract: An adapter allows to connect two electronic devices at the same port, at the same time. The device allows to actuate two devices at one single port which originally allows the connection of one single device. The adapter device includes a primary connector 2 to be connected to a host device taking up said adapter device, a secondary connector 4 to take up the memory card 3, an interrupter S1 connecting the primary connector and the secondary connector, and a device interface circuit 51 connected to the primary connector and controlling the opening and closing of the interrupter S1 depending on the commands arriving at the primary connector.

Abstract: The invention is a portable host machine comprising a smart card and a connector. The connector has a set of pads able to communicate through a first protocol. The smart card has at least a first pad able to communicate using a second protocol. The connector has at least an additional pad able to communicate using the second protocol. The first and additional pads are privately linked into said portable host machine.

Abstract: The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of writing, within a configuration device of each memory circuit included in the stack, a piece of information on an identifier allocated to the memory circuit in the stack, and a piece of information on the results of the validity test of the memory circuit. The invention also relates to a method for addressing a memory circuit, to a stack of memory circuits, and to an electronic device including such a stack.

Abstract: In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the wafer. The wafer is polarized such that an attempt to thin the wafer from the backside results in at least one selected from a group consisting of destruction of the wafer and damage to the wafer.

Abstract: The components of performance analysis considered within the scope of the invention are, in particular, the determination of the speed at which a circuit or a circuit component can generate output signals from input signals, and the noise immunity of the circuit. The process for evaluating the performance of a very high scale integrated circuit comprises: a first step (E1) in which, for each lead (Li) of said circuit, an equivalent coupling capacity value (CTi) relative a fixed potential, is generated as being a sum of the existing real coupling capacity values (Cij) of leads (Lj) of said circuit with said lead (Li), each of which is assigned a weighting coefficient (Kij); and a second step (E2) following said first step (E1), in which a switching time interval ([tid,tif]) in each lead (Li) is generated as being a function of said equivalent capacity (CTi). The fixed potential may be ground.

Abstract: In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two numbers A and B and the result S. Each number A and B and the result S is divided into K groups each of m bits, and one parity bit is associated with each group. In accordance with the invention, the parity PS associated with the result S is obtained at the same time as the result. The input carry bit c.sub.i n intervening in the addition is available before the beginning of operations. Consequently, it is used in a first stage 10' upstream of the device, which calculates intermediate variables p.sub.i,j and g.sub.i,j. The other input carry bits c.sub.i,1 corresponding to the other groups are determined only later by a carry look ahead circuit, and consequently they are used only in a second stage 50' downstream of the device. The use of c.sub.

Abstract: A system as proposed for calculating the parity bits (PS) of a sum (S) of two numbers (A, B). One parity bit (PA, PB, PS) is associated with each group of m bits (a.sub.i, b.sub.i, s.sub.i) extracted from the numbers (A, B) and the sum (S). For each group, one system for calculating the parity bit (PC) associated with the corresponding group extracted from the carry word formed at the time of the addition is provided. This system includes the following:a first stage (11) for calculating, for every i included between 1 and m-1, the values:p.sub.i =a.sub.i .sym.b.sub.ig.sub.i =a.sub.i .multidot.b.sub.iwhere .sym. indicates the EXCLUSIVE OR operation.a first operator (41a) for calculating, for every i included between 1 and m-1, the values P.sub.i and the values G.sub.i verifying the following recurring logical equations:P.sub.i =p.sub.i .multidot.P.sub.i-1, with P.sub.1 =p.sub.1G.sub.i =g.sub.i +p.sub.i .multidot.G.sub.i-1, with G.sub.1 =g.sub.1a second operator (41b) for calculating the following:Y=G.sub.1 .