Patents by Inventor Michelle Jen
Michelle Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11669481Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: GrantFiled: December 22, 2021Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
-
Publication number: 20220308954Abstract: In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2021Publication date: September 29, 2022Inventors: Swadesh Choudhary, Debendra Das Sharma, Michelle Jen
-
Publication number: 20220114128Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
-
Patent number: 11232058Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: GrantFiled: August 29, 2019Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
-
Patent number: 11163717Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: July 6, 2020Date of Patent: November 2, 2021Assignee: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Publication number: 20210056067Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: July 6, 2020Publication date: February 25, 2021Applicant: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Patent number: 10747688Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.Type: GrantFiled: December 22, 2016Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Venkatraman Iyer, Tao Liang
-
Patent number: 10706003Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: February 4, 2019Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Publication number: 20190384733Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
-
Publication number: 20190303338Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: February 4, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Patent number: 10198394Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: October 1, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Publication number: 20180181502Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Michelle Jen, Debendra Das Sharma, Venkatraman Iyer, Tao Liang
-
Publication number: 20170344512Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: October 1, 2016Publication date: November 30, 2017Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
-
Publication number: 20060294327Abstract: A device includes a first memory that includes a page in progress field. A read processing engine is connected to the first memory. The read processing engine to interleave read requests based on the page in progress field.Type: ApplicationFiled: June 23, 2005Publication date: December 28, 2006Inventors: Debendra Sharma, Lesley Chang, Michelle Jen
-
Publication number: 20050223123Abstract: Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be generated from data read requests stored in a first-in-first-out in a first order. The read entries are stored in a storage device and each read entry identifies internal data reads to read data to service the data read request to which the read entry corresponds. A controller coupled to the storage structure may then submit the internal data reads a central arbiter to read data in a second order that is different than the first order. Moreover, the controller also allows the second order to include internal data reads from one read entry, before a completing servicing of another partially serviced read entry, thus providing “simultaneous” servicing of several read entries.Type: ApplicationFiled: March 31, 2004Publication date: October 6, 2005Inventors: Michelle Jen, Debendra Sharma