Abstract: An image segmentation apparatus, preferably integrally implemented in a device such as an FPGA, including a buffer memory for storing pixel data, a digital filter in communication with the buffer memory, the digital filter having programmable coefficients, a histogram generating module in communication with the buffer memory that generates a histogram of the pixel data, a statistics generating module in communication with the buffer memory that generates statistics regarding the pixel data, a threshold select module for selecting one of a plurality thresholds and an apply threshold module for applying the selected threshold to data stored in the buffer to generate exceedance data that exceed the selected threshold. In a preferred embodiment, a control module controls each of the buffer, histogram, statistics and threshold modules to control data flow, program filter coefficients and select the appropriate threshold.

Abstract: An image segmentation apparatus, preferably integrally implemented in a device such as an FPGA, including a buffer memory for storing pixel data, a digital filter in communication with the buffer memory, the digital filter having programmable coefficients, a histogram generating module in communication with the buffer memory that generates a histogram of the pixel data, a statistics generating module in communication with the buffer memory that generates statistics regarding the pixel data, a threshold select module for selecting one of a plurality thresholds and an apply threshold module for applying the selected threshold to data stored in the buffer to generate exceedance data that exceed the selected threshold. In a preferred embodiment, a control module controls each of the buffer, histogram, statistics and threshold modules to control data flow, program filter coefficients and select the appropriate threshold.