Patents by Inventor Michelle Steen
Michelle Steen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080083697Abstract: A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.Type: ApplicationFiled: October 15, 2007Publication date: April 10, 2008Inventors: Timothy Dalton, Michelle Steen
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Publication number: 20080026551Abstract: An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.Type: ApplicationFiled: July 30, 2007Publication date: January 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Chester Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam Shahidi, Michelle Steen, Clement Wann
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Publication number: 20070281431Abstract: A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.Type: ApplicationFiled: August 17, 2007Publication date: December 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn Biery, Ghavam Shahidi, Michelle Steen
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Publication number: 20070152273Abstract: A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUNISESS MACHINES CORPORATIONInventors: Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Young-Hee Kim, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen, Ying Zhang
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Publication number: 20070152276Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Arnold, Glenn Biery, Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Michael Gribelyuk, Young-Hee Kim, Barry Linder, Vijay Narayanan, Joseph Newbury, Vamsi Paruchuri, Michelle Steen
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Publication number: 20070138563Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: ApplicationFiled: December 16, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Alessandro Callegari, Michael Chudzik, Bruce Doris, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen
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Publication number: 20070032010Abstract: A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.Type: ApplicationFiled: August 2, 2005Publication date: February 8, 2007Applicant: International Business Machines CorporationInventors: Glenn Biery, Ghavam Shahidi, Michelle Steen
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Publication number: 20060027934Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: October 3, 2005Publication date: February 9, 2006Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
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Publication number: 20060022280Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.Type: ApplicationFiled: July 14, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Chester Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam Shahidi, Michelle Steen, Clement Wann
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Publication number: 20060006476Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.Type: ApplicationFiled: July 6, 2004Publication date: January 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn Biery, Michelle Steen
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Publication number: 20050121768Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
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Publication number: 20050112896Abstract: A multi-bit phase change memory cell including a stack of a plurality of conductive layers and a plurality of phase change material layers, each of the phase change material layers disposed between a corresponding pair of conductive layers and having electrical resistances that are different from one another.Type: ApplicationFiled: November 20, 2003Publication date: May 26, 2005Applicant: International Business Machines CorporationInventors: Hendrik Hamann, Chung Lam, Michelle Steen, Hon-Sum Wong
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Publication number: 20050092676Abstract: A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.Type: ApplicationFiled: October 30, 2003Publication date: May 5, 2005Inventors: Timothy Dalton, Michelle Steen
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Publication number: 20050037608Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.Type: ApplicationFiled: August 13, 2003Publication date: February 17, 2005Inventors: Panayotis Andricacos, Emanuel Cooper, Timothy Dalton, Hariklia Deligianni, Daniel Guidotti, Keith Kwietniak, Michelle Steen, Cornelia Tsang