Patents by Inventor Michelle Y. Che

Michelle Y. Che has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof
    Patent number: 8095781
    Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: January 10, 2012
    Assignee: Verisilicon Holdings Co., Ltd.
    Inventors: Vijayanand Angarai, Michelle Y. Che, Asheesh Kashyap, Tracy Nguyen
  • INSTRUCTION FETCH PIPELINE FOR SUPERSCALAR DIGITAL SIGNAL PROCESSORS AND METHOD OF OPERATION THEREOF
    Publication number: 20100058039
    Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 4, 2010
    Applicant: VeriSilicon Holdings Company, Limited
    Inventors: Vijayanand Angarai, Michelle Y. Che, Asheesh Kashyap, Tracy Nguyen