Abstract: Aspects of the present disclosure are directed to fabrication methods for analogue quantum systems (AQSs). Further aspects of the present disclosure are directed to methods for solving computational problems using an AQS. Methods for fabricating an AQS include generating a Hamiltonian based on a computational problem, which may be an optimization problem or a simulation problem. Further, the method includes identifying AQS fabrication parameters based on one or more identified measurement methods and the Hamiltonian. Lastly, an AQS can be fabricated based on the identified fabrication parameters. An AQS may be used inter alia to simulate a battery or interfaces.

Abstract: Quantum processing element and method to perform logic operations on a quantum processing element are disclosed. The quantum processing element includes: a semiconductor, a dielectric material forming an interface with the semiconductor, a plurality of dopant dots embedded in the semiconductor, each of the dopant dots comprising one or more dopant atoms and one or more electrons or holes confined within the dopant dots, wherein spin of an unpaired electron or hole of each dopant dot forms at least one qubit. The method includes the step of: controlling orientation of nuclear spins of the one or more dopant atoms in a pair of dopant dots and/or controlling a hyperfine interaction between nuclear spins of one or more dopant atoms and electron or hole spins of the unpaired electron or hole in the pair of dopant dots to perform a quantum logic operation on a corresponding pair of qubits.

Abstract: A quantum bit, quantum processing element, and one or more large-scale quantum processing systems are disclosed. the quantum bit includes: a first quantum dot embedded in the semiconductor substrate, the first quantum dot comprising a first donor atom cluster and a second quantum dot embedded in the semiconductor substrate, the second quantum dot comprising a second donor atom cluster. The first and second quantum dots share a single electron, and the quantum bit is electrically controlled utillising the hyperfine interaction between the single electron and one or more nuclear spins present in the first and second donor atom clusters.

Abstract: Aspects of the present disclosure are directed to quantum processing systems that include a plurality of donor atom qubits positioned in a semiconductor substrate. The system also comprises a plurality of control gates configured to control the donor atom qubits. The system further comprises an SLQD charge sensor fabricated on/in the semiconductor substrate. The SLQD charge sensor is configured to sense spin-states of two or more donor atom qubits, which are positioned within a sensing range of the SLQD charge sensor.

Abstract: A quantum processing element is disclosed. The element includes a semiconductor substrate, a dielectric material forming an interface with the semiconductor substrate, and a donor molecule embedded in the semiconductor. The donor molecule includes a plurality of dopant dots embedded in the semiconductor, each dopant dot includes one or more dopant atoms, and one or more electrons/holes confined to the dopant dots. A distance between the dopant dots is between 3 and 9 nanometres.

Abstract: A method for readout of a singlet-triplet qubit in a donor based quantum processing element is disclosed. The method includes: initialising the singlet-triplet qubit in a ground state |G; performing a shelving readout; using a final measured charge configuration of the singlet-triplet qubit to determine information about a current Zeeman energy difference; and using the information about the current Zeeman energy difference to adjust mapping of the shelving readout.

Abstract: A method for measuring the spin of an electron in a quantum dot that is tunnel coupled to a reservoir is disclosed. The method includes measuring a spin state of the injected electron while applying a ramped detuning for a time period.

Abstract: One-dimensional and two-dimensional arrays of qubits are disclosed. The one-dimensional array includes two or more double-quantum dots embedded in silicon, the two or more double-quantum dots arranged in an Echelon formation, such that the distance between the two or more double-quantum dots is approximately 40 nm and the distance between the two quantum dots in each double-quantum dot is approximately 12 nm; two or more reservoirs to load electrons to the corresponding two or more double-quantum dots to form singlet-triplet qubits in each double-quantum dot; and two or more gates for controlling the formed singlet-triplet qubits. The two-dimensional array of qubits includes two or more layers of vertically-stacked one-dimensional arrays of qubits.

Abstract: The present disclosure provides methods for fabricating multi-layered electronic architectures in silicon and/or germanium. In particular the disclosure provides an advanced marker design and a methodology for aligning devices on multiple layers of a multi-layered electronic architecture. The disclosure also provides a process for growing a semiconductor material with high quality surfaces.

Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.

Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.

Abstract: The present disclosure provides methods for fabricating multi-layered electronic architectures in silicon and/or germanium. In particular the disclosure provides an advanced marker design and a methodology for aligning devices on multiple layers of a multi-layered electronic architecture. The disclosure also provides a process for growing a semiconductor material with high quality surfaces.

Abstract: The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.

Abstract: The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.

Abstract: This invention concerns the fabrication of nanoscale and atomic scale devices. The method involves creating one or more registration markers. Using a SEM or optical microscope to form an image of the registration markers and the tip of a scanning tunnelling microscope (STM). Using the image to position and reposition the STM tip to pattern the device structure. Forming the active region of the device and then encapsulating it such that one or more of the registration markers are still visible to allow correct positioning of surface electrodes. The method can be used to form any number of device structures including quantum wires, single electron transistors, arrays or gate regions. The method can also be used to produce 3D devices by patterning subsequent layers with the STM and encapsulating in between.

Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.

Abstract: Individual hydrogen atoms are desorbed from a hydrogen terminated layer on a silicon substrate, using an STM tip, to form a pattern of exposed regions. A single donor-bearing molecule (such as phosphorous atoms). The spins of the donor atoms may be used as qubits in a slid quantum computer.

Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.