Abstract: A QP detection unit includes digital circuit elements. There is provided a digital QP detector which detects an electric power signal Vi, which is an input signal, and outputs a detection signal Vo. The digital QP detector includes a register which records input digital data, a first multiplier which multiplies the digital data recorded in the register by a first coefficient, a second multiplier which multiplies the digital data recorded in the register by a second coefficient, an adder which adds the electric power signal Vi and the output from the first multiplier to each other, a comparator which compares the level of the electric power signal Vi and the level of the detection signal Vo, and a first switch which switches the digital data to be fed to the register between the output from the adder (Vi>Vo) and the output from the second multiplier (Vi<Vo) based on a comparison result of the comparator.

Abstract: A QP detection unit includes digital circuit elements. There is provided a digital QP detector which detects an electric power signal Vi, which is an input signal, and outputs a detection signal Vo. The digital QP detector includes a register which records input digital data, a first multiplier which multiplies the digital data recorded in the register by a first coefficient, a second multiplier which multiplies the digital data recorded in the register by a second coefficient, an adder which adds the electric power signal Vi and the output from the first multiplier to each other, a comparator which compares the level of the electric power signal Vi and the level of the detection signal Vo, and a first switch which switches the digital data to be fed to the register between the output from the adder (Vi>Vo) and the output from the second multiplier (Vi<Vo) based on a comparison result of the comparator.

Abstract: A properly level-controlled digital signal can be obtained every sample. An input signal is supplied to amplifiers having their gains of one, two, four and eight. Outputs of the amplifiers are converted to digital signals at the same time in corresponding A/D converters having the same characteristic, respectively, and inputted to a data selection part. In the data selection part, when an input signal is high level, one A/D converter to which is inputted the input signal passing through the corresponding amplifier having its large gain, overflows so that the overflow-bit thereof becomes “1”. The output digital signal of the A/D converter is selected and outputted, which is connected to the amplifier having the largest gain among the amplifiers connected to corresponding A/D converters each of which has its overflow-bit is “0”. The digital signal is corrected in its scale and outputted.

Abstract: A properly level-controlled digital signal can be obtained every sample. An input signal is supplied to amplifiers having their gains of one, two, four and eight. Outputs of the amplifiers are converted to digital signals at the same time in corresponding A/D converters having the same characteristic, respectively, and inputted to a data selection part. In the data selection part, when an input signal is high level, one A/D converter to which is inputted the input signal passing through the corresponding amplifier having its large gain, overflows so that the overflow-bit thereof becomes “1”. The output digital signal of the A/D converter is selected and outputted, which is connected to the amplifier having the largest gain among the amplifiers connected to corresponding A/D converters each of which has its overflow-bit is “0”. The digital signal is corrected in its scale and outputted.

Abstract: The offset QPSK modulation analytic system capable of estimating the initial phase of an offset QPSK modulated signal is disclosed. For each of a plurality of candidate values for the initial phase, the correlation coefficient between a signal whose clock delay has been estimated and compensated and an ideal signal generated based on the signal is computed, and the candidate value having the maximum value of the computed correlation coefficient is estimated as the optimum initial phase.

Abstract: A method for automatically setting a reference level is provided. A frequency-converted output of frequency converter 13 is branched and the branched output is further frequency-converted by another frequency converter 33. The thus frequency-converted signal is converted to a digital signal by an AD converter 31 and the digital signal is once stored in a memory 35. The digital data is read out from the memory 35 and a check is made to see if the AD converter 31 was overflown. If the AD converter 31 was overflown, an attenuation amount of a first stage attenuator 12 is increased from an initially set value to acquire a data again. If the AD converter 31 was not overflown, a check is made to see if a peak value of the digital data is within a range of 85%-65% of the full scale of the AD converter 31. If a peak value of the digital data is not within the range of 85%-65% of the full scale, a calculation is performed to increase/decrease the gain of an amplifier 15.