Abstract: A clock input circuit includes a switch circuit, a switching circuit, and a programmable register to provide switching control based on the level of a power supply voltage of a microcomputer. When the power supply voltage of the microcomputer is equal to or higher than a predetermined value, general noise removal is conducted through two Schmitt trigger circuit and a capacitor. When the power supply voltage of the microcomputer is lower than the predetermined value, noise removal is conducted through a Schmitt trigger circuit, and two flip-flops. Thus, noise removal of high accuracy can be realized, independent of the power supply voltage of the microcomputer.

Abstract: In a flash memory write mode, a microcomputer operation mode setting circuit sets a mode setting signal at one level. At this stage, a voltage drop caused by an LPF formed of a resistor, an inductor, and a capacitor can be suppressed at a low level. In a mode other than the flash memory write mode, the microcomputer operation mode setting circuit sets the mode setting signal at another level. At this stage, high frequency noise can be removed by the LPF formed of the resistor, the inductor, and the capacitor.

Abstract: A ROM data verification circuit has a DMAC (2) for reading out data stored in the ROM (1) when a CPU (3) abandons to use an address bus (5) and a data bus (6), for dividing the data read into a plurality of divided data, and for outputting the divided data into a plurality of output ports (4) designated by addresses generated by the DMAC (2).

Abstract: A ROM data read protect circuit according to the present invention comprises a non-volatile memory that stores a data for allowing or inhibiting reading of the ROM data and a logic circuit for control for controlling allowing or inhibiting of an operation for reading of data in a ROM according to the data stored in the non-volatile memory. When "0" is written in a first storage area of the non-volatile memory reading of the ROM data is inhibited, and when "0" is written in a second storage area of the non-volatile memory reading of the ROM data is allowed. A data can be written anytime in the first storage area but data can not be deleted from the first storage, so that the read inhibit mode is always effected in the initial state. A data can be written in the second storage area only when specific setting is executed but can not be deleted from the second storage.

Abstract: A motor control apparatus which comprises: a central processing unit which executes general control of processing of the motor control apparatus, a timer portion which generates predetermined pulses from a reference clock signal, a plurality of registers provided corresponding to control signals of respective phases in which data can be reloaded by the central processing unit, shift registers which are able to store the data having the same number of bits as the number of the registers and the values of plurality of registers can be reloaded to the shift registers by the predetermined pulses output from the timer portion, and a control signal generator means which generates control signals of respective phases of a polyphase motor.