Abstract: A semiconductor device which can make the generation of gate parasitic oscillations more difficult than a semiconductor device of the related art is provided.

Abstract: A vertical-type FET includes: a semiconductor layer having a plurality of trenches; a gate electrode partially embedded in the trenches; and a base region and a source region that are formed in the semiconductor layer between adjacent trenches. The gate electrode includes: a plurality of first gate structures respectively formed in the plurality of trenches, wherein each first gate structure has a protruding portion protruding from the trench and an embedded portion embedded in the trench; and a second gate structure formed to connect between the protruding portions of adjacent first gate structures. The embedded portion is formed on a side wall of the trench through a first insulating film. The second gate structure is formed on the source region through a second insulating film thicker than the first insulating film.

Abstract: A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.

Abstract: A semiconductor device having bonding pad electrode or electrodes of a multi-layer structure. The bonding pad electrode comprises a lower electrode layer formed on a semiconductor substrate, and a cover insulating film formed on the lower electrode layer. The cover insulating film has an opening for exposing at least a portion of the lower electrode layer. A step portion is provided at a side wall of the opening of the cover insulating film. The size of the opening at the upside portion of a step surface of the step portion is larger than the size of the opening at the downside portion of the step surface. The bonding pad electrode further comprises an upper electrode layer formed on the portion of the lower electrode layer exposed via the opening. The upper electrode layer is made of material having corrosion resistance against the substance which is corrosive to the lower electrode layer, and the upper electrode layer overlaps the step surface of the step portion.

Abstract: At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Abstract: A semiconductor device is provided which has a structure being suitable for scale-down of cells and is capable of, without an increase in channel resistance, improving a resistance property against device breakdown required when a semiconductor device breaks down due to inverse voltages applied. In the above semiconductor device, a source region narrowing section, in which width dimension on a plane of a source region is partially limited, is formed at the cell corner section disposed on diagonal lines and in a vicinity of the diagonal lines.

Abstract: At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Abstract: A semiconductor device having bonding pad electrode or electrodes of a multi-layer structure. The bonding pad electrode comprises a lower electrode layer formed on a semiconductor substrate, and a cover insulating film formed on the lower electrode layer. The cover insulating film has an opening for exposing at least a portion of the lower electrode layer. A step portion is provided at a side wall of the opening of the cover insulating film. The size of the opening at the upside portion of a step surface of the step portion is larger than the size of the opening at the downside portion of the step surface. The bonding pad electrode further comprises an upper electrode layer formed on the portion of the lower electrode layer exposed via the opening. The upper electrode layer is made of material having corrosion resistance against the substance which is corrosive to the lower electrode layer, and the upper electrode layer overlaps the step surface of the step portion.

Abstract: A buried gate type power field effect transistor has a drain layer forming a lower part of a silicon substrate, a base layer forming another part of the silicon substrate on the lower part, a source region forming a surface portion of the silicon substrate on the another part, a gate insulating layer covering an inner surface of a groove penetrating from the surface of the silicon substrate through the source region and the base region into the drain region and a polysilicon gate electrode filling the secondary groove defined by the gate insulating layer, wherein the gate electrode is formed with a recess exposed to the upper surface thereof and covered with an insulating layer defining a secondary recess filled with a piece of polysilicon so as to reduce the effective width of the gate electrode, thereby creating the upper surface substantially coplanar with the surface of the source region in spite of an etch back carried on a polysilicon layer for forming the gate electrode.