Patents by Inventor Michiaki TAMAKAWA
Michiaki TAMAKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10256196Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.Type: GrantFiled: June 30, 2016Date of Patent: April 9, 2019Assignee: J-DEVICES CORPORATIONInventors: Kiminori Ishido, Michiaki Tamakawa, Toshihiro Iwasaki
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Patent number: 9837382Abstract: Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.Type: GrantFiled: April 4, 2016Date of Patent: December 5, 2017Assignee: J-DEVICE CORPORATIONInventors: Shinji Watanabe, Toshihiro Iwasaki, Michiaki Tamakawa
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Patent number: 9635762Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: GrantFiled: July 20, 2015Date of Patent: April 25, 2017Assignee: J-DEVICES CORPORATIONInventors: Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Hiroshi Demachi, Takeshi Miyakoshi, Tomoshige Chikai, Kiminori Ishido, Hiroaki Matsubara, Takashi Nakamura, Hirokazu Honda, Yoshikazu Kumagaya, Shotaro Sakumoto, Toshihiro Iwasaki, Michiaki Tamakawa
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Patent number: 9553052Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.Type: GrantFiled: December 9, 2015Date of Patent: January 24, 2017Assignee: J-DEVICES CORPORATIONInventors: Hiroaki Matsubara, Toshihiro Iwasaki, Tomoshige Chikai, Kiminori Ishido, Shinji Watanabe, Michiaki Tamakawa
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Publication number: 20170005044Abstract: The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.Type: ApplicationFiled: June 30, 2016Publication date: January 5, 2017Inventors: Kiminori ISHIDO, Michiaki TAMAKAWA, Toshihiro IWASAKI
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Publication number: 20160300779Abstract: Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.Type: ApplicationFiled: April 4, 2016Publication date: October 13, 2016Inventors: Shinji WATANABE, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160172580Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.Type: ApplicationFiled: December 9, 2015Publication date: June 16, 2016Inventors: Hiroaki MATSUBARA, Toshihiro IWASAKI, Tomoshige CHIKAI, Kiminori ISHIDO, Shinji WATANABE, Michiaki TAMAKAWA
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Patent number: 9368474Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: GrantFiled: September 10, 2015Date of Patent: June 14, 2016Assignee: J-DEVICES CORPORATIONInventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160079204Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160027715Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: ApplicationFiled: July 20, 2015Publication date: January 28, 2016Inventors: Shinji WATANABE, Sumikazu HOSOYAMADA, Shingo NAKAMURA, Hiroshi DEMACHI, Takeshi MIYAKOSHI, Tomoshige CHIKAI, Kiminori ISHIDO, Hiroaki MATSUBARA, Takashi NAKAMURA, Hirokazu HONDA, Yoshikazu KUMAGAYA, Shotaro SAKUMOTO, Toshihiro IWASAKI, Michiaki TAMAKAWA