Patents by Inventor Michiari Kawano
Michiari Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8507377Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: GrantFiled: April 21, 2010Date of Patent: August 13, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20100240211Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: ApplicationFiled: April 21, 2010Publication date: September 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA
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Patent number: 7755169Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: January 22, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20090127666Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: January 22, 2009Publication date: May 21, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA, Junichi Mitani
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Patent number: 7498659Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: February 13, 2006Date of Patent: March 3, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 7241676Abstract: After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.Type: GrantFiled: September 24, 2004Date of Patent: July 10, 2007Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Michiari Kawano
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Patent number: 7129565Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: January 24, 2003Date of Patent: October 31, 2006Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 7119439Abstract: After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.Type: GrantFiled: June 5, 2003Date of Patent: October 10, 2006Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Michiari Kawano
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Publication number: 20060194124Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: February 13, 2006Publication date: August 31, 2006Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20050042816Abstract: After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.Type: ApplicationFiled: September 24, 2004Publication date: February 24, 2005Inventors: Kenichi Watanabe, Michiari Kawano
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Patent number: 6794244Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.Type: GrantFiled: June 19, 2002Date of Patent: September 21, 2004Assignee: Fujitsu LimitedInventors: Kazuhiro Mizutani, Michiari Kawano
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Publication number: 20030227089Abstract: After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.Type: ApplicationFiled: June 5, 2003Publication date: December 11, 2003Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Michiari Kawano
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Publication number: 20030173675Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: January 24, 2003Publication date: September 18, 2003Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada, Junichi Mitani
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Publication number: 20020153548Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.Type: ApplicationFiled: June 19, 2002Publication date: October 24, 2002Applicant: FUJITSU LIMITEDInventors: Kazuhiro Mizutani, Michiari Kawano
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Patent number: 6433381Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.Type: GrantFiled: January 9, 2001Date of Patent: August 13, 2002Assignee: Fujitsu LimitedInventors: Kazuhiro Mizutani, Michiari Kawano
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Publication number: 20020014648Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.Type: ApplicationFiled: January 9, 2001Publication date: February 7, 2002Applicant: Fujitsu Limited,Inventors: Kazuhiro Mizutani, Michiari Kawano
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Patent number: 5661340Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.Type: GrantFiled: October 26, 1993Date of Patent: August 26, 1997Assignee: Fujitsu LimitedInventors: Taiji Ema, Masaaki Higashitani, Toshimi Ikeda, Michiari Kawano, Hiroshi Nomura, Masaya Katayama, Masahiro Kuwamura
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Patent number: 4833519Abstract: A method and apparatus are disclosed for improving step coverage of a wiring layer of a semiconductor device especially at the contact holes thereof. The inside of the contact holes are covered by a polysilicon layer deposited by chemical vapor deposition (CVD), and selectively doped with impurities having the same conductivity type as the contact region which the polysilicon layer contacts at the bottom of the contact hole. The remaining part of the contact hole is buried with SiO.sub.2, and the wiring layer is formed on it. Since the step coverage of the material deposited by CVD is very good, the disconnection at the side walls of the contact hole is avoided. Further, short circuits caused by growth of spikes of eutectic of silicon and aluminum is also avoided. If the surface of the polysilicon layer is covered with a thin film of SiO.sub.2 or Si.sub.3 N.sub.4, the material to bury the contact hole may be replaced by other materials such as polysilicon or amorphous silicon.Type: GrantFiled: May 15, 1987Date of Patent: May 23, 1989Assignee: Fujitsu LimitedInventors: Michiari Kawano, Masayuki Higashimoto, Shigeo Kashiwagi, Jun Nakano, Osamu Shimizu