Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.

Abstract: The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.