Patents by Inventor Michihiko Ichinose
Michihiko Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6747361Abstract: A semiconductor chip semiconductor device of the present invention is capable of obtaining a high-quality bare chip (HQC) easily and can retain quality without being affected by the surrounding environment. Electrodes formed on the surface of a first resin sealed package for sealing a semiconductor chip are connected to the electrodes of the semiconductor chip and each electrode comprises a mounting area to be connected to an object to be mounted and a testing area for connecting testing equipment.Type: GrantFiled: July 24, 2001Date of Patent: June 8, 2004Assignee: NEC Electronics CorporationInventor: Michihiko Ichinose
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Patent number: 6611063Abstract: A method for forming a mold-encapsulated semiconductor device includes the steps of mounting a semiconductor chip on a metallic plate having a metallic interconnect pattern thereon, encapsulating the semiconductor chip on the metallic interconnect pattern, removing the bottom of the metallic plate by etching to expose the metallic interconnect pattern, and forming external terminals on the bottom of the metallic interconnect pattern. The method reduces the thickness as well as the planar dimensions of the semiconductor device.Type: GrantFiled: September 18, 2000Date of Patent: August 26, 2003Assignee: NEC Electronics CorporationInventors: Michihiko Ichinose, Tomoko Takizawa, Hirokazu Honda, Keiichirou Kata
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Patent number: 6538305Abstract: A semiconductor device includes an interposing substrate having a top surface mounting thereon a semiconductor chip and a bottom surface mounting thereon a solder ball islands. Chip electrodes of the semiconductor chip are connected to the solder ball islands through a top interconnect pattern, via holes and a bottom interconnect pattern. The second interconnect pattern has a solder-flow damping/stopping pattern in the vicinity of the solder ball islands for stopping the solder from flowing onto the bottom interconnect pattern upon melting.Type: GrantFiled: July 25, 2001Date of Patent: March 25, 2003Assignee: NEC CorporationInventor: Michihiko Ichinose
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Patent number: 6504244Abstract: A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern. The wiring tape is adhered to at least the top, bottom and one side of a semiconductor chip. The semiconductor device has outer connecting portions arranged on the above surface of the chip. The semiconductor device is comparable in package size with a bare chip. A semiconductor module having a plurality of such semiconductor devices arranged bidimensionally or tridimensionally achieves desirable electric characteristics while obviating the dense arrangement of a number of wirings.Type: GrantFiled: January 31, 2001Date of Patent: January 7, 2003Assignee: NEC CorporationInventors: Michihiko Ichinose, Tomoko Takizawa
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Publication number: 20020014683Abstract: A semiconductor device includes an interposing substrate having a top surface mounting thereon a semiconductor chip and a bottom surface mounting thereon a solder ball islands. Chip electrodes of the semiconductor chip are connected to the solder ball islands through a top interconnect pattern, via holes and a bottom interconnect pattern. The second interconnect pattern has a solder-flow damping/stopping pattern in the vicinity of the solder ball islands for stopping the solder from flowing onto the bottom interconnect pattern upon melting.Type: ApplicationFiled: July 25, 2001Publication date: February 7, 2002Applicant: NEC CorporationInventor: Michihiko Ichinose
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Publication number: 20020011651Abstract: A semiconductor chip semiconductor device of the present invention is capable of obtaining a high-quality bare chip (HQC) easily and can retain quality without being affected by the surrounding environment. Electrodes formed on the surface of a first resin sealed package for sealing a semiconductor chip are connected to the electrodes of the semiconductor chip and each electrode comprises a mounting area to be connected to an object to be mounted and a testing area for connecting testing equipment.Type: ApplicationFiled: July 24, 2001Publication date: January 31, 2002Applicant: NEC CORPORATIONInventor: Michihiko Ichinose
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Publication number: 20010010396Abstract: A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern. The wiring tape is adhered to at least the top, bottom and one side of a semiconductor chip. The semiconductor device has outer connecting portions arranged on the above surfaces of the chip. The semiconductor device is comparable in package size with a bare chip. A semiconductor module having a plurality of such semiconductor devices arranged bidimensionally or tridimensionally achieves desirable electric characteristics while obviating the dense arrangement of a number of wirings.Type: ApplicationFiled: January 31, 2001Publication date: August 2, 2001Inventors: Michihiko Ichinose, Tomoko Takizawa
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Patent number: 6265760Abstract: In a semiconductor device, semiconductor chips are mounted on two surfaces of a die pad. A lower one of the semiconductor chips has a portion projecting outward from an upper one of the semiconductor chips. The semiconductor chips are connected to integrally molded external connection leads trough wiring members. The lower semiconductor chipping the outwardly projecting portion has, on its surface on the same side as an upper surface of the upper semiconductor chip, pads to be connected to the external connection leads. A semiconductor device lead frame and a method of manufacturing the same are also disclosed.Type: GrantFiled: April 29, 1999Date of Patent: July 24, 2001Assignee: NEC CorporationInventors: Takehito Inaba, Michihiko Ichinose, Kenji Oyachi
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Patent number: 6259152Abstract: A hybrid leadframe has first conductive leads extending into space over a semiconductor chip and second conductive leads outside the space, the first conductive leads and the second conductive leads are connected through bonding wires to bonding pads on the semiconductor chip, and the first conductive leads are directly adhered to insulating adhesive compound layers spread on predetermined area of the upper surface of the semiconductor device, wherein the second conductive leads are bifurcated so that one of the bifurcated portions is connected through the bonding wire to the bonding pad and the other bifurcated portion is adhered to the insulating adhesive compound layers so as to enhance the stability of the second conductive lead.Type: GrantFiled: April 30, 1999Date of Patent: July 10, 2001Assignee: NEC CorporationInventors: Hiromitsu Takeda, Michihiko Ichinose, Takehito Inaba, Ken Fukamachi
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Patent number: 6246117Abstract: A semiconductor device of a BGA (Ball-Grid-Array) package comprises a lead frame, a semiconductor chip, bonding wires, a plastic, an insulation film, and solder balls. The semiconductor chip is mounted on one side of the lead frame, and is electrically connected to the lead frame by the bonding wires. The plastic encapsulates the semiconductor chip and the bonding wires. The insulation film has openings for exposing predetermined regions of the lead frame. The insulation film is affixed onto an underside surface of the lead frame. The solder balls act as connection terminals. The solder balls are formed on the regions of the lead frame exposed through the openings in the insulation film.Type: GrantFiled: December 14, 1999Date of Patent: June 12, 2001Assignee: NEC CorporationInventor: Michihiko Ichinose
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Patent number: 6215169Abstract: In a semiconductor device, the adhesive layer of a tape that is adhered to the surface of a chip is disposed so that there is no overlap with an aperture in the uppermost surface of a semiconductor element. With the usual type of tape, the tape is kept at a distance of at least 0.1 mm from the cover aperture in the surface of the semiconductor element, and in the case in which there are two covers, the tape is kept at a distance of at least 0.1 mm from an aperture at the uppermost surface of the semiconductor element. The aperture includes either a fuse aperture or a bonding bad and fuse aperture.Type: GrantFiled: May 13, 1999Date of Patent: April 10, 2001Assignee: NEC CorporationInventor: Michihiko Ichinose
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Patent number: 6211573Abstract: There is provided an adhering structure between a semiconductor chip and two alignments of first side inner leads and second side inner leads extending in first and second sides of the semiconductor chip respectively. Each of the first and second side inner leads has a stitched portion. The first and second sides are separated by a center line of the semiconductor chip. The semiconductor chip and the first and second side inner leads are adhered to each other by first and second side electrically insulative adhesive tapes respectively. Each of the first and second side electrically insulative adhesive tapes has both surfaces with adhesion force. The first and second side electrically insulative adhesive tapes extend on first and second inner stripe regions so as to adhere the stitched portions of the first and second side inner leads respectively.Type: GrantFiled: June 12, 1998Date of Patent: April 3, 2001Assignee: NEC CorporationInventor: Michihiko Ichinose
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Patent number: 6166443Abstract: Internal electrodes and external lead wiring lines are formed on the front surface of a substrate of a semiconductor device, and solder bumps electrically connected to the external lead wiring lines via through holes are provided on the rear surface of the substrate. A first semiconductor chip is mounted on the surface of the substrate, and a second semiconductor chip is mounted on the rear surface of the substrate. Electrodes of the first semiconductor chip are connected to bonding pads at one side ends of the internal wiring lines, and electrodes of the second semiconductor chip are connected to the bonding pads at the other ends of the internal wiring lines and the external lead wiring lines with bonding wires passing through openings provided in the substrate.Type: GrantFiled: April 27, 1999Date of Patent: December 26, 2000Assignee: NEC CorporationInventors: Takehito Inaba, Michihiko Ichinose, Kenji Oyachi