Patents by Inventor Michihiko Mifuji
Michihiko Mifuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230298805Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: April 13, 2023Publication date: September 21, 2023Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 11657953Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: April 14, 2021Date of Patent: May 23, 2023Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Publication number: 20210233700Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 11011297Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: February 27, 2020Date of Patent: May 18, 2021Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Publication number: 20200203058Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 10622443Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: July 20, 2016Date of Patent: April 14, 2020Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
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Patent number: 10141500Abstract: A magnetoelectric converting element includes a substrate, a magnetosensitive layer, a first insulating layer, an underlying conductive layer, a second insulating layer, and a terminal conductor. The magnetosensitive layer is formed on the substrate. The first insulating layer is formed with first opening for exposing a part of the magnetosensitive layer. The underlying conductive layer is formed on the exposed part of the magnetosensitive layer. The second insulating layer is formed with a second opening for exposing a part of the underlying conductive layer. The terminal conductor is formed on the exposed part of the underlying conductive layer. The second opening is arranged to be located inside the first opening in plan view.Type: GrantFiled: July 3, 2017Date of Patent: November 27, 2018Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Satoshi Nakagawa
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Publication number: 20180013058Abstract: A magnetoelectric converting element includes a substrate, a magnetosensitive layer, a first insulating layer, an underlying conductive layer, a second insulating layer, and a terminal conductor. The magnetosensitive layer is formed on the substrate. The first insulating layer is formed with first opening for exposing a part of the magnetosensitive layer. The underlying conductive layer is formed on the exposed part of the magnetosensitive layer. The second insulating layer is formed with a second opening for exposing a part of the underlying conductive layer. The terminal conductor is formed on the exposed part of the underlying conductive layer. The second opening is arranged to be located inside the first opening in plan view.Type: ApplicationFiled: July 3, 2017Publication date: January 11, 2018Inventors: Isamu NISHIMURA, Michihiko MIFUJI, Satoshi NAKAGAWA
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Publication number: 20170287624Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Applicant: ROHM CO., LTD.Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 9697948Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: November 10, 2014Date of Patent: July 4, 2017Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Patent number: 9673144Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.Type: GrantFiled: December 21, 2015Date of Patent: June 6, 2017Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
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Patent number: 9585254Abstract: An electronic device includes a semiconductor substrate, an electronic element mounted on the substrate, a conductive layer electrically connected to the electronic element, a sealing resin and a columnar conductor. The substrate has a recess formed in its obverse surface. The electronic element is mounted on the bottom surface of the recess. The conductive layer has an obverse-surface contacting region located on the obverse surface of the substrate. The sealing resin is disposed in at least a part of the recess for covering at least a part of the obverse surface of the substrate. The columnar conductor is electrically connected to the obverse-surface contacting region of the conductive layer and exposed from the sealing resin at a side opposite to the obverse surface of the substrate.Type: GrantFiled: February 4, 2016Date of Patent: February 28, 2017Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Hideaki Yanagida, Michihiko Mifuji, Yasuhiro Fuwa
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Publication number: 20160329399Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Applicant: ROHM CO., LTD.Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
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Patent number: 9425203Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: June 10, 2015Date of Patent: August 23, 2016Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
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Publication number: 20160242292Abstract: An electronic device includes a semiconductor substrate, an electronic element mounted on the substrate, a conductive layer electrically connected to the electronic element, a sealing resin and a columnar conductor. The substrate has a recess formed in its obverse surface. The electronic element is mounted on the bottom surface of the recess. The conductive layer has an obverse-surface contacting region located on the obverse surface of the substrate. The sealing resin is disposed in at least a part of the recess for covering at least a part of the obverse surface of the substrate. The columnar conductor is electrically connected to the obverse-surface contacting region of the conductive layer and exposed from the sealing resin at a side opposite to the obverse surface of the substrate.Type: ApplicationFiled: February 4, 2016Publication date: August 18, 2016Inventors: Isamu NISHIMURA, Hideaki YANAGIDA, Michihiko MIFUJI, Yasuhiro FUWA
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Publication number: 20160111365Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Applicant: ROHM CO., LTD.Inventors: lsamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
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Patent number: 9257387Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.Type: GrantFiled: August 12, 2015Date of Patent: February 9, 2016Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
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Publication number: 20150348900Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Applicant: ROHM CO., LTD.Inventors: lsamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
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Publication number: 20150279848Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Applicant: ROHM CO., LTD.Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
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Patent number: 9136216Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.Type: GrantFiled: February 14, 2014Date of Patent: September 15, 2015Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio