Abstract: In a semiconductor integrated circuit device including a nonvolatile memory device and a semiconductor integrated circuit board which are mounted on a wiring board where the nonvolatile memory is enable to electrically program data therein at a first voltage and the semiconductor integrated circuit board is operable at a second voltage lower than the first voltage, the nonvolatile memory device has a first terminal supplied with the first voltage and a second terminal for outputting the second voltage, the semiconductor integrated circuit board has a third terminal which is electrically connected to the second terminal. The nonvolatile memory device includes a voltage converting circuit, disposed between the first terminal and the second terminal, for converting the first voltage into the second voltage. The nonvolatile memory device is stacked on the semiconductor integrated circuit board.

Abstract: In a semiconductor integrated circuit device including a nonvolatile memory device and a semiconductor integrated circuit board which are mounted on a wiring board where the nonvolatile memory is enable to electrically program data therein at a first voltage and the semiconductor integrated circuit board is operable at a second voltage lower than the first voltage, the nonvolatile memory device has a first terminal supplied with the first voltage and a second terminal for outputting the second voltage, the semiconductor integrated circuit board has a third terminal which is electrically connected to the second terminal. The nonvolatile memory device includes a voltage converting circuit, disposed between the first terminal and the second terminal, for converting the first voltage into the second voltage. The nonvolatile memory device is stacked on the semiconductor integrated circuit board.

Abstract: A data processor having: a peripheral circuit for selecting one of input terminals such as input channels, processing input data from the selected input terminal, requesting the transfer of the processing result, and outputting identification information (CH2 to CH0) which permits the identification of the selected input terminal; and a data transfer control circuit comprising a destination address register (DAR) with its low-order bits variable according to the identification information from the peripheral circuit, whereby the low-order bits of destinations can be controlled by the peripheral circuit in the transfer control circuit. The peripheral circuit is not required to comprise data registers for storing an input data processing result for each input terminal in one-to-one correspondence with the input terminals.