Patents by Inventor Michihiro Kanno
Michihiro Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088159Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: August 21, 2023Publication date: March 14, 2024Inventors: Naoya Kasahara, Michihiro Kanno
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Patent number: 11798951Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: GrantFiled: October 26, 2021Date of Patent: October 24, 2023Assignee: Sony Group CorporationInventors: Naoya Kasahara, Michihiro Kanno
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Publication number: 20220173127Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: October 26, 2021Publication date: June 2, 2022Inventors: Naoya Kasahara, Michihiro Kanno
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Patent number: 11195860Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: GrantFiled: February 21, 2020Date of Patent: December 7, 2021Assignee: Sony Group CorporationInventors: Naoya Kasahara, Michihiro Kanno
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Publication number: 20200357827Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: February 21, 2020Publication date: November 12, 2020Inventors: Naoya Kasahara, Michihiro Kanno
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Patent number: 10593704Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: GrantFiled: July 11, 2018Date of Patent: March 17, 2020Assignee: Sony CorporationInventors: Naoya Kasahara, Michihiro Kanno
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Patent number: 10504923Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: GrantFiled: July 11, 2018Date of Patent: December 10, 2019Assignee: Sony CorporationInventors: Naoya Kasahara, Michihiro Kanno
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Publication number: 20180350846Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: July 11, 2018Publication date: December 6, 2018Inventors: Naoya Kasahara, Michihiro Kanno
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Publication number: 20180350845Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: July 11, 2018Publication date: December 6, 2018Inventors: Naoya Kasahara, Michihiro Kanno
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Patent number: 10115739Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: GrantFiled: April 24, 2015Date of Patent: October 30, 2018Assignee: Sony CorporationInventors: Naoya Kasahara, Michihiro Kanno
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Publication number: 20180175071Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.Type: ApplicationFiled: April 24, 2015Publication date: June 21, 2018Inventors: Naoya Kasahara, Michihiro Kanno
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THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY UNIT AND ELECTRONIC APPARATUS
Publication number: 20150179811Abstract: There are provided a thin film transistor having a simple structure that allows reduction in leakage current at the time of gate negative bias, and a method of manufacturing the thin film transistor, and a display unit and an electronic apparatus. The thin film transistor includes: a gate electrode; a semiconductor film including a channel region that faces the gate electrode; and an insulating film provided at least at a position near an end portion on the gate electrode side of side walls of the semiconductor film.Type: ApplicationFiled: August 2, 2013Publication date: June 25, 2015Applicant: Sony CorporationInventors: Michihiro Kanno, Takahiro Kawamura -
Publication number: 20150097163Abstract: A semiconductor device includes: a gate electrode layer; a gate insulating film provided on the gate electrode layer; a semiconductor layer provided, in opposition to the gate electrode layer, on the gate insulating film; and a source-drain electrode layer provided on the semiconductor layer and on the gate insulating film. A face, in opposition to the gate insulating film, of the semiconductor layer is located above a face of a section, located on the gate insulating film, of the source-drain electrode layer.Type: ApplicationFiled: April 15, 2013Publication date: April 9, 2015Inventors: Michihiro Kanno, Takahiro Kawamura, Hiroshi Inamura
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Publication number: 20110073860Abstract: A thin film transistor comprising an insulating film, a gate electrode embedded in a superficial portion of the insulating film, a gate insulating film on the gate electrode and the insulating film, a semiconductor film on the gate insulating film, a channel protection film on a portion of the semiconductor film with end surfaces which have a forward tapered slope, a first electrode on the semiconductor film which mounts onto one tapered side of the channel protection film, and a second electrode on the semiconductor film which mounts onto the other tapered side of the channel protection film, where an edge of the gate electrode closest to the first electrode is offset towards the second electrode from the point where the first electrode abuts the semiconductor film.Type: ApplicationFiled: September 21, 2010Publication date: March 31, 2011Applicant: SONY CORPORATIONInventors: Michihiro Kanno, Takahiro Kawamura
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Patent number: 7601579Abstract: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.Type: GrantFiled: December 5, 2007Date of Patent: October 13, 2009Assignee: Sony CorporationInventor: Michihiro Kanno
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Patent number: 7439118Abstract: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.Type: GrantFiled: February 17, 2006Date of Patent: October 21, 2008Assignee: Sony CorporationInventor: Michihiro Kanno
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Publication number: 20080085578Abstract: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.Type: ApplicationFiled: December 5, 2007Publication date: April 10, 2008Applicant: SONY CORPORATIONInventor: Michihiro Kanno
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Publication number: 20060189075Abstract: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETS, and the memory array part having N-type and P-type FETS, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.Type: ApplicationFiled: February 17, 2006Publication date: August 24, 2006Inventor: Michihiro Kanno