Patents by Inventor Michihiro Onoda

Michihiro Onoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142324
    Abstract: A torque detection device includes a first yoke and a first magnetic guide member. A first opposing portion of the first magnetic guide member overlaps with a first-yoke ring of the first yoke when the first-yoke ring is projected onto the first opposing portion in an axial direction. Furthermore, the first opposing portion overlaps with an inner surface of a second tubular portion when the inner surface is projected onto the first opposing portion in the axial direction. A housing distance, which is a shortest distance measured from the first opposing portion to the inner surface, is longer than a yoke distance, which is a shortest distance measured from the first opposing portion to the first-yoke ring.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Toshiro SUZUKI, Michihiro MAKITA, Koichiro MATSUMOTO, Kazuhiro YOSHINO, Norihisa KOIDE, Nagisa ONODA
  • Patent number: 9054185
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: June 9, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Michihiro Onoda
  • Publication number: 20140021546
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode.
    Type: Application
    Filed: June 11, 2013
    Publication date: January 23, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Michihiro Onoda
  • Publication number: 20120081645
    Abstract: Above a semiconductor substrate on which switching semiconductor elements are formed respectively corresponding to a plurality of pixels, a first and a second copper wiring layers and thereon an aluminum reflection electrode layer are arranged. Wirings and first and second light shielding layers are formed by patterning the copper wiring layers and pluralities of first and second openings are formed respectively in the first and the second light shielding layers. The first openings and the second openings are shifted in two directions not to overlap each other in a plan view. The wiring layers and the light shielding layers are formed of copper while restraining dishing.
    Type: Application
    Filed: June 28, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tetsuo Yoshimura, Michihiro Onoda
  • Patent number: 7939397
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor pattern which is covered with a first insulating film over a first active region, forming a second semiconductor pattern over a second active region, forming a second insulating film over the first insulating film and the first and second semiconductor patterns, forming an opening whose depth reaches the first semiconductor pattern by etching the second insulating film and the first insulating film, forming sidewalls on side surfaces of the second semiconductor pattern by patterning the second insulating film, forming a metal film over the first and second semiconductor patterns respectively, and forming silicide layers by reacting the first and second semiconductor patterns with the metal film.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 10, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michihiro Onoda, Takayuki Matsumoto
  • Publication number: 20090280613
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor pattern which is covered with a first insulating film over a first active region, forming a second semiconductor pattern over a second active region, forming a second insulating film over the first insulating film and the first and second semiconductor patterns, forming an opening whose depth reaches the first semiconductor pattern by etching the second insulating film and the first insulating film, forming sidewalls on side surfaces of the second semiconductor pattern by patterning the second insulating film, forming a metal film over the first and second semiconductor patterns respectively, and forming silicide layers by reacting the first and second semiconductor patterns with the metal film.
    Type: Application
    Filed: January 29, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Michihiro ONODA, Takayuki MATSUMOTO
  • Publication number: 20060154433
    Abstract: A semiconductor device having: a semiconductor substrate; a plurality of semiconductor elements formed in the semiconductor substrate; a metal wiring made of a first metal layer and formed above the semiconductor substrate; a lower electrode made of the first metal layer and formed above the semiconductor substrate; a dielectric film formed on the lower electrode in a shape withdrawing from a periphery of the lower electrode; and an upper electrode formed on the dielectric film in a shape withdrawing from a periphery of the dielectric film, wherein the lower electrode, the dielectric film and the upper electrode form a MIM capacitor element. There are provided a semiconductor device having a MIM capacitor element capable of suppressing leak current as much as possible, and its manufacture method.
    Type: Application
    Filed: May 18, 2005
    Publication date: July 13, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Michihiro Onoda