Abstract: A method for manufacturing a semiconductor device and a cleaning device for stripping resist provide semiconductor device with superior element characteristic in a sufficient yield, in such away that, after dry etching of the lithography process, wet cleaning removes resists, and particles or metal impurities are made to sufficiently remove without damaging fine pattern. The method for manufacturing the semiconductor device comprises: forming a resist pattern on a film provided for the semiconductor substrate, forming a fine pattern of conductive film while performing dry etching using the resist pattern as a mask, stripping the resist pattern by single-wafer system treatment upon supplying resist stripping liquid to fine pattern forming surface of the semiconductor substrate, and carrying out rinse treatment of the semiconductor substrate.

Abstract: A manufacturing method of the present invention comprises the steps of patterning to form a gate electrode pattern as well as an oxide film pattern by applying dry etching to a layered film which is formed, on a semiconductor substrate, of an oxide film and a SiGe film, being laid in this order; a first cleaning wherein, after the step of the patterning, the semiconductor substrate is cleaned with a first cleaning solution containing hydrofluoric acid; and a second cleaning wherein, after the step of the first cleaning, the semiconductor substrate is cleaned with a second cleaning solution containing ammonia and hydrogen peroxide.

Abstract: The present invention enables reduction of a film thickness of a protection film so as to eliminate destruction caused by stress of the protection film; to increase a film thickness of an organic insulation film so as to exhibit the function of the organic insulation film sufficiently; and to reduce irregularities of the protection film thickness. In the organic insulation film 18 formation method according to the present invention, an organic insulation film 18, a protection film 20, and a metal film are successively formed in this order on a substrate 10. On the metal film, a patterned photo-resist is formed so as to be used as a mask for etching the metal film. The remaining metal film is used as a mask when etching the protection film 20 and the organic insulation film 18. The protection film 20 can significantly reduce its thickness because the protection film 20 need not be used as a mask. The organic insulation film 18 can be set to an arbitrary thickness regardless of the protection film 20.

Abstract: A manufacturing method of the present invention comprises the steps of patterning to form a gate electrode pattern as well as an oxide film pattern by applying dry etching to a layered film which is formed, on a semiconductor substrate, of an oxide film and a SiGe film, being laid in this order; a first cleaning wherein, after the step of the patterning, the semiconductor substrate is cleaned with a first cleaning solution containing hydrofluoric acid; and a second cleaning wherein, after the step of the first cleaning, the semiconductor substrate is cleaned with a second cleaning solution containing ammonia and hydrogen peroxide.

Abstract: The present invention enables to reduce a film thickness of a protection film so as to eliminate destruction caused by stress of the protection film; to increase a film thickness of an organic insulation film so as to exhibit the function of the organic insulation film sufficiently; and to reduce irregularities of the protection film thickness.

Abstract: On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.