Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: A liquid crystal display (LCD) device having a side backlight unit that minimizes or eliminates extraneous bright lines on the LCD panel. The side backlight unit includes a lamp reflector and lamp disposed on a light incident side surface of a light guide plate. A light reflection layer is formed on the inner surface of the lamp reflector, and a transparent protective layer is formed on the reflection layer. The transparent protective layer has a thickness less than 5 micrometers. The lamp reflector has arm portions that sandwich the light guide plate on the front and back surfaces at the lamp side of the light guide plate. A light transmission region between the arm portions of the lamp reflector and the front and back surfaces of the light guide plate has a thickness less than 5 micrometers.

Abstract: The present invention provides a method of alignment between sheet materials, a method of alignment, a substrate assembling method, and an aligning apparatus, which are capable of easily and surely performing highly accurate alignment and suppressing a reduction in material yield.

Abstract: A method for aligning a lenticular sheet, in accordance with the present invention, includes applying curable adhesive to a surface and placing a lenticular sheet over the curable adhesive on the surface. The adhesive is cured at a first end portion of the lenticular sheet such that the first end portion is aligned with a first reference position. A temperature of the lenticular sheet is adjusted to align a second end portion of the lenticular sheet with a second reference position. Remaining portions of adhesive are cured to secure the lenticular sheet.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: A voltage application driving method is provided for quickly changing the alignment of a liquid crystal layer in thin film transistor liquid crystal displays (TFT/LCD) to a bend alignment. In this driving method, a potential difference larger than 10 V is continuously or intermittently provided between the signal electrode of the liquid crystal cells, and the counter electrode of the display while maintaining the potential difference between the gate electrode and the signal electrode of the cells larger than 10 V.