Patents by Inventor Michiko Takei

Michiko Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9244878
    Abstract: A handheld electronic device and display method for a handheld electronic device provide for an initialization screen to be displayed by a display unit, in response to user input, to display symbols reflecting an intent of the user. The handheld electronic device includes a user input unit having a first key to which a symbol of a first type is allocated and a symbol of a second type is not allocated, and a second key to which a symbol of the first type and a symbol of the second type are both allocated; a display unit that, upon input via the user input unit, displays a symbol of the first type and/or a symbol of the second type; and a control unit that controls what the display unit displays.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 26, 2016
    Assignee: KYOCERA CORPORATION
    Inventor: Michiko Takei
  • Patent number: 9177974
    Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Patent number: 9076718
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 7, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 9035295
    Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 19, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
  • Patent number: 9024311
    Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 5, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshimasa Chikama, Kazuo Nakagawa, Yoshifumi Ohta, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Miyajima, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20140367683
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 18, 2014
    Inventors: Yoshifumi OHTA, Go MORI, Hirohiko NISHIKI, Yoshimasa CHIKAMA, Tetsuya AITA, Masahiko SUZUKI, Okifumi NAKAGAWA, Michiko TAKEI, Yoshiyuki HARUMOTO, Takeshi HARA
  • Patent number: 8865516
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: October 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 8829513
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8823002
    Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: September 2, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Tohru Okabe, Tetsuya Aita, Tsuyoshi Inoue, Yoshiyuki Harumoto, Takeshi Yaneda
  • Patent number: 8779478
    Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi
  • Patent number: 8730173
    Abstract: Provided is an electronic device which easily selects and executes an application relating to characters inputted by a user. A cellular phone is provided with a display unit which displays a character input screen, an operation unit for inputting characters to be displayed on the character input screen, and a control unit which controls the display unit to display a candidate for conversion or a predicted candidate of the characters inputted using the operation unit. The control unit displays the name of an application or the name of a processing in the application as the candidate for conversion or a predicted candidate, and when either name is selected, executes the processing of the application corresponding to the selected name.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 20, 2014
    Assignee: Kyocera Corporation
    Inventors: Shuuji Ishikawa, Yasumasa Sekigami, Takafumi Oka, Hiroyuki Bamba, Michiko Takei, Nayu Noumachi
  • Patent number: 8723802
    Abstract: Provided is a mobile electronic device capable of reflecting a user's intention. While an initial screen for waiting for an incoming-call is being displayed on an LCD display unit, a control unit performs control so that a first type character display area and a second type character display area are displayed on the LCD display unit in place of the initial screen, wherein the first type character display area is an area for, when any of first keys is depressed, displaying a first type character (for example, a number such as “1”, “2”, “3”) assigned to the depressed first key and the second type character display area is an area for displaying a second type character (for example, “a”, “i”, “u”, etc. in Japanese Hiragana letter) assigned to the depressed first key.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: May 13, 2014
    Assignee: Kyocera Corporation
    Inventors: Kouji Watanabe, Yuuki Wada, Michiko Takei, Yuka Ishizuka, Tomoyasu Takahashi, Takafumi Satou, Masao Inadome, Hideko Murakami
  • Patent number: 8685803
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8629874
    Abstract: It is possible to provide a mobile display device which can improve usability even when the character size is increased for improving visibility. A method for controlling the mobile display device is also disclosed. A control unit (18) can set a conversion candidate of an input character displayed on a second display region (conversion candidate character display region (162)) of a display unit (16) to a first display mode (normal mode) for displaying the conversion candidate in a first character size and to a second display mode (enlarged mode) for displaying the conversion candidate in a second character size greater than the first character size while differentiating a display priority of a plurality of conversion candidates to be displayed in the second display region in the first display mode and a display priority of a plurality of conversion candidates to be displayed in the second display region in the second display mode.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: January 14, 2014
    Assignee: Kyocera Corporation
    Inventors: Natsuhito Honda, Hiroshi Tsuruta, Tomoyuki Urano, Michiko Takei
  • Patent number: 8530899
    Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 10, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Harumoto, Takeshi Hara, Tohru Okabe, Takeshi Yaneda, Tetsuya Aita, Tsuyoshi Inoue, Michiko Takei
  • Publication number: 20130193430
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Application
    Filed: March 29, 2010
    Publication date: August 1, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130175521
    Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.
    Type: Application
    Filed: May 23, 2011
    Publication date: July 11, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi
  • Publication number: 20130140552
    Abstract: A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 6, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshifumi Ohta, Takeshi Hara, Hinae Mizuno
  • Publication number: 20130134411
    Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).
    Type: Application
    Filed: April 5, 2011
    Publication date: May 30, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
  • Patent number: 8441016
    Abstract: Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: May 14, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsuyoshi Inoue, Tohru Okabe, Tetsuya Aita, Michiko Takei, Yoshiyuki Harumoto, Takeshi Yaneda